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AT6003ALV-4AC

Description
IC FPGA 4NS 144TQFP
Categorysemiconductor    Programmable logic devices   
File Size416KB,29 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

AT6003ALV-4AC Overview

IC FPGA 4NS 144TQFP

AT6003ALV-4AC Parametric

Parameter NameAttribute value
Number of logic elements/units1600
Number of I/Os120
Number of gates9000
Voltage - Power3.135 V ~ 3.465 V
Installation typesurface mount
Operating temperature0°C ~ 70°C
Package/casing144-LQFP
Supplier device packaging144-LQFP(20x20)
Features
High-performance
– System Speeds > 100 MHz
– Flip-flop Toggle Rates > 250 MHz
– 1.2 ns/1.5 ns Input Delay
– 3.0 ns/6.0 ns Output Delay
Up to 204 User I/Os
Up to 6,400 Registers
Cache Logic
®
Design
– Complete/Partial In-System Reconfiguration
– No Loss of Data or Machine State
– Adaptive Hardware
Low Voltage and Standard Voltage Operation
– 5.0 (V
CC
= 4.75V to 5.25V)
– 3.3 (V
CC
= 3.0V to 3.6V)
Automatic Component Generators
– Reusable Custom Hard Macro Functions
Very Low-power Consumption
– Standby Current of 500 µA/ 200 µA
– Typical Operating Current of 15 to 170 mA
Programmable Clock Options
– Independently Controlled Column Clocks
– Independently Controlled Column Resets
– Clock Skew Less Than 1 ns Across Chip
Independently Configurable I/O (PCI Compatible)
– TTL/CMOS Input Thresholds
– Open Collector/Tristate Outputs
– Programmable Slew-rate Control
– I/O Drive of 16 mA (combinable to 64 mA)
Coprocessor
Field
Programmable
Gate Arrays
AT6000(LV)
Series
Description
AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal for
use as reconfigurable coprocessors and implementing compute-intensive logic.
Supporting system speeds greater than 100 MHz and using a typical operating current
of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive
designs. These FPGAs are designed to implement Cache Logic, which provides the
user with the ability to implement adaptive hardware and perform hardware
acceleration.
The patented AT6000 Series architecture employs a symmetrical grid of small yet
powerful cells connected to a flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is surrounded by programmable
I/O.
AT6000 Series Field Programmable Gate Arrays
Device
Usable Gates
Cells
Registers (maximum)
I/O (maximum)
Typ. Operating Current (mA)
Cell Rows x Columns
AT6002*
6,000
1,024
1,024
96
15 - 30
32 x 32
AT6003*
9,000
1,600
1,600
120
25 - 45
40 x 40
AT6005
15,000
3,136
3,136
108
40 - 80
56 x 56
(continued)
AT6010
30,000
6,400
6,400
204
85 - 170
80 x 80
Obsolete: Not
Recommended for
New Design
AT6000LV Series
AT6002*
AT6003*
Atmel-0264G-FPGA-AT6000(LV)-Datasheet_042015
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