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ATF1504ASVL-20JI44

Description
IC CPLD 64MC 20NS 44PLCC
Categorysemiconductor    Programmable logic devices   
File Size557KB,31 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
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ATF1504ASVL-20JI44 Overview

IC CPLD 64MC 20NS 44PLCC

ATF1504ASVL-20JI44 Parametric

Parameter NameAttribute value
Programmable typeIn-system programmable (minimum 10,000 program/erase cycles)
Delay time tpd(1) maximum20ns
Supply voltage - internal3 V ~ 3.6 V
Number of macro cells64
Number of I/Os32
Operating temperature-40°C ~ 85°C(TA)
Installation typesurface mount
Package/casing44-LCC (J-lead)
Supplier device packaging44-PLCC(16.59x16.59)
Features
High-density, High-performance, Electrically-erasable Complex
Programmable Logic Device
– 3.0 to 3.6V Operating Range
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44, 68, 84, 100 Pins
– 15 ns Maximum Pin-to-pin Delay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open-collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
Advanced Power Management Features
– Automatic 5 µA Standby for “L” Version
– Pin-controlled 100 µA Standby Mode (Typical)
– Programmable Pin-keeper Circuits on Inputs and I/Os
– Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
Security Fuse Feature
Green (Pb/Halide-free/RoHS Compliant) Package Options
Low-voltage,
Complex
Programmable
Logic Device
ATF1504ASV
ATF1504ASVL
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent-latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
V
CC
Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Rev. 1409J–PLD–6/05
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