ATF1508AS-10JI84 datasheet, PDF

Datasheet> All Categories > semiconductor> Programmable logic devices> ATF1508AS-10JI84

ATF1508AS-10JI84: DescriptionIC CPLD 128MC 10NS 84PLCC; Categorysemiconductor Programmable logic devices; File Size714KB，31 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

Download Datasheet Parametric View All

ATF1508AS-10JI84 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	ATF1508AS-10JI84	-	-	View	Buy Now

ATF1508AS-10JI84 Overview

IC CPLD 128MC 10NS 84PLCC

ATF1508AS-10JI84 Parametric

Parameter Name	Attribute value
Programmable type	In-system programmable (minimum 10,000 program/erase cycles)
Delay time tpd(1) maximum	10ns
Supply voltage - internal	4.5 V ~ 5.5 V
Number of macro cells	128
Number of I/Os	64
Operating temperature	-40°C ~ 85°C（TA）
Installation type	surface mount
Package/casing	84-LCC (J-lead)
Supplier device packaging	84-PLCC（29.31x29.31）

Preview

Download Datasheet

View All

Features

•

High-density, High-performance, Electrically-erasable Complex

Programmable Logic Device

– 128 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 84, 100, 160 Pins

– 7.5 ns Maximum Pin-to-pin Delay

– Registered Operation up to 125 MHz

– Enhanced Routing Resources

Flexible Logic Macrocell

– D/T/Latch Configured Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register within a COM Output

Advanced Power Management Features

– Automatic 10 µA Standby for “L” Version

– Pin-controlled 1 mA Standby Mode

– Programmable Pin-keeper Inputs and I/Os

– Reduced-power Feature per Macrocell

Available in Commercial and Industrial Temperature Ranges

Available in 84-lead PLCC, 100-lead PQFP, 100-lead TQFP and 160-lead PQFP Packages

Advanced EE Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

Fast In-System Programmability (ISP) via JTAG

PCI-compliant

3.3 or 5.0V I/O Pins

Security Fuse Feature

Green (Pb/Halide-free/RoHS Compliant) Package Options

•

High-

performance

EE PLD

ATF1508AS

ATF1508ASL

•

Enhanced Features

•

Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

Output Enable Product Terms

Transparent-latch Mode

Combinatorial Output with Registered Feedback within Any Macrocell

Three Global Clock Pins

ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

Fast Registered Input from Product Term

Programmable “Pin-keeper” Option

Power-up Reset Option

Pull-up Option on JTAG Pins TMS and TDI

Advanced Power Management Features

– Edge-controlled Power-down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts

Rev. 0784P–PLD–7/05

Description

The ATF1508AS is a high-performance, high-density complex programmable logic device

(CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 128 logic macrocells

and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic

PLDs. The ATF1508AS’s enhanced routing switch matrices increase usable gate count and

increase odds of successful pin-locked design modifications.

The ATF1508AS has up to 96 bi-directional I/O pins and four dedicated input pins, depending

on the type of device package selected. Each dedicated pin can also serve as a global control

signal, register clock, register reset or output enable. Each of these control signals can be

selected for use individually within each macrocell.

Each of the 128 macrocells generates a buried feedback that goes to the global bus. Each

input and I/O pin also feeds into the global bus. The switch matrix in each logic block then

selects 40 individual signals from the global bus. Each macrocell also generates a foldback

logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1508AS

allows fast, efficient generation of complex logic functions. The ATF1508AS contains eight

such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product

terms.

The ATF1508AS macrocell, shown in Figure 1, is flexible enough to support highly-complex

logic functions operating at high speed. The macrocell consists of five sections: product terms

and product term select multiplexer; OR/XOR/CASCADE logic, a flip-flop, output select and

enable, and logic array inputs.

Unused macrocells are automatically disabled by the compiler to decrease power consump-

tion. A security fuse, when programmed, protects the contents of the ATF1508AS. Two bytes

(16 bits) of User Signature are accessible to the user for purposes such as storing project

name, part number, revision or date. The User Signature is accessible regardless of the state

of the security fuse.

The ATF1508AS device is an in-system programmable (ISP) device. It uses the industry-stan-

dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-

scan Description Language (BSDL). ISP allows the device to be programmed without remov-

ing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also

allows design modifications to be made in the field via software.

Product Terms and

Select Mux

Each ATF1508AS macrocell has five product terms. Each product term receives as its inputs

all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as needed to

the macrocell logic gates and control signals. The PTMUX programming is determined by the

design compiler, which selects the optimum macrocell configuration.

OR/XOR/

CASCADE Logic

The ATF1508AS’s logic structure is designed to efficiently support all types of logic. Within a

single macrocell, all the product terms can be routed to the OR gate, creating a 5-input

AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be

expanded to as many as 40 product terms with a little small additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-

tions. One input to the XOR comes from the OR sum term. The other XOR input can be a

product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input

allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimiza-

tion of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.

ATF1508AS(L)

0784P–PLD–7/05

ATF1508AS(L)

Flip-flop

The ATF1508AS’s flip-flop has very flexible data and control functions. The data input can

come from either the XOR gate, from a separate product term or directly from the I/O pin.

Selecting the separate product term allows creation of a buried registered feedback within a

combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-

ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-

through latch. In this mode, data passes through when the clock is high and is latched when

the clock is low.

The clock itself can be either the Global CLK Signal (GCK) or an individual product term. The

flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock,

one of the macrocell product terms can be selected as a clock enable. When the clock enable

function is active and the enable signal (product term) is low, all clock edges are ignored. The

flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product

term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchro-

nous preset (AP) can be a product term or always off.

Extra Feedback

The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The

extra buried feedback signal can be either combinatorial or a registered signal regardless of

whether the output is combinatorial or registered. (This enhancement function is automatically

implemented by the fitter software.) Feedback of a buried combinatorial output allows the cre-

ation of a second latch within a macrocell.

The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-

vidually configured as an input, output or for bi-directional operation. The output enable for

each macrocell can be selected from the true or compliment of the two output enable pins, a

subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done

by the fitter software when the I/O is configured as an input, all macrocell resources are still

available, including the buried feedback, expander and cascade logic.

The global bus contains all input and I/O pin signals as well as the buried feedback signal from

all 128 macrocells. The switch matrix in each logic block receives as its inputs all signals from

the global bus. Under software control, up to 40 of these signals can be selected as inputs to

the logic block.

Each macrocell also generates a foldback product term. This signal goes to the regional bus

and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell’s

product terms. The 16 foldback terms in each region allows generation of high fan-in sum

terms (up to 21 product terms) with a little additional delay.

The ATF1508AS device has two sets of V

pins viz, V

CCINT

and V

CCIO

. V

CCINT

pins must

always be connected to a 5.0V power supply. V

CCINT

pins are for input buffers and are “com-

patible” with both 3.3V and 5.0V inputs. V

CCIO

pins are for I/O output drives and can be

connected for 3.3/5.0V power supply.

This option enables the device output to provide control signals such as an interrupt that can

be asserted by any of the several devices.

I/O Control

Global Bus/Switch

Matrix

Foldback Bus

3.3V or 5.0V I/O

Operation

Open-collector

Output Option

0784P–PLD–7/05

Recommended Resources

Switching power supply circuit diagram composed of FA500

Electrician scale electrical schematic circuit (3)

Gain programmable differential input and output amplifier circuit

555 three-digit display capacitance meter circuit

Broadband amplifier circuit with conversion speed of 600v/us

TTL crystal calibrator

LPC1114 oscillator and clock issues: Dear experts:I don't understand the oscillator of LPC1114. Please answer my questions. Thanks!Question: 1. The manual says that LPC1114 has 3 independent oscillators: system oscillator, IRC and watchd...; evenaye NXP MCU

Does anyone have the Chinese and English manual for the Agilent E4438C?: Does anyone have the Chinese and English manual for the Agilent E4438C? Please help me, kind brothers and sisters, thank you~:)...; 笑对人生8714 RF/Wirelessly

【GD32450I-EVAL】Onboard SDRAM supports LittleVGL: Previous programs only supported internal RAM, which was too small for a 480*272 screen. To support the entire screen, a 480*272*4-byte space must be allocated, a total of 510K. The onboard chip ends ...; tinnu GD32 MCU

Common EDA tool software operation guide: ...; wkj PCB Design

TI Industry Week series of seminars are coming, register to watch the live broadcast and win multiple gifts!: [font=微软雅黑][size=3]Event details: [url=https://www.eeworld.com.cn/huodong/TI_Industry/index.html]https://www.eeworld.com.cn/huodong/TI_Industry/index.html[/url] Event time:TI Industrial Week is coming...; EEWORLD社区 TI Technology Forum

Laptop touchpad: Why can the touchpad of a laptop only be used when it is in contact with the skin? I have tried using paper, iron, eraser, etc. but nothing works. I don't know if this is a common problem or just mine...; cs123cs123 Microcontroller MCU

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components