This X25128 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
ICmic
TM
IC MICROSYSTEMS
128K
2
X25128
SPI Serial E PROM with Block Lock
TM
16K x 8 Bit
Protection
FEATURES
•
2MHz Clock Rate
•
SPI Modes (0,0 & 1,1)
•
16K X 8 Bits
—32 Byte Page Mode
•
Low Power CMOS
—<1µA Standby Current
—<5mA Active Current
•
2.7V To 5.5V Power Supply
•
Block Lock Protection
2
—Protect 1/4, 1/2 or all of E PROM Array
•
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Enable Latch
—Write Protect Pin
•
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
•
High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
•
14-Lead SOIC Package
•
16-Lead SOIC Package
•
8-Lead PDIP Package
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
DESCRIPTION
2
The X25128 is a CMOS 131,072-bit serial E PROM,
internally organized as 16K x 8. The X25128 features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus.
The bus signals are a clock input (SCK) plus separate data
in (SI) and data out (SO) lines. Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same
bus.
The X25128 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25128 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as a
hardwire input to the X25128 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25128 utilizes Xicor’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X DECODE
LOGIC
16K BYTE
ARRAY
128
16 X 256
SO
SI
SCK
CS
COMMAND
DECODE
AND
CONTROL
LOGIC
128
16 X 256
HOLD
256
32 X 256
WP
WRITE
CONTROL
AND
TIMING
LOGIC
32
8
Y DECODE
DATA REGISTER
3091 FM F01
©Xicor
Inc. 1994, 1995, 1996 Patents Pending
3091-2.9 5/14/97 T2/C0/D2 SH
1
Characteristics subject to change without notice
X25128
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the
clock input, while data on the SO pin change after the
falling edge of the clock input.
Chip Select (CS)
When CS is high, the X25128 is deselected and the
SO output pin is at high impedance and unless an
internal write operation is underway, the X25128 will
be in the standby power mode. CS low enables the
X25128, placing it in the active power mode. It should
be noted that after power-up, a high to low transition
on CS is required prior to the start of any operation.
Write Protect (WP)
When WP is low and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25128 status register are
disabled, but the part otherwise functions normally.
When WP is held high, all functions, including nonvola-
tile writes operate normally. WP going low while CS is
still low will interrupt a write to the X25128 status
register. If the internal write cycle has already been
initiated, WP going low will have no effect on a write.
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25128 in a system with WP pin grounded and still
be able to write to the status register. The WP pin func-
tions will be enabled when the WPEN bit is set “0”.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought low while SCK is Low. To resume commu-
nication, HOLD is brought high, again while SCK is
low. If the pause feature is not used, HOLD should be
held high at all times.
PIN CONFIGURATION
Not to scale
14 Lead SOIC
CS
SO
NC
.344”
NC
NC
WP
VSS
1
2
3
4
5
6
7
.244”
16 Lead SOIC
CS
SO
NC
.394”
NC
NC
NC
WP
VSS
1
2
3
4
5
6
7
8
.244”
8 Lead PDIP
CS
SO
WP
VSS
1
2
3
4
.325”
X25128
8
7
6
5
VCC
HOLD
SCK
SI
3091 FM 02
14
13
12
X24128
11
10
9
8
VCC
HOLD
NC
NC
NC
SCK
SI
16
15
14
X25128
13
12
11
10
9
VCC
HOLD
NC
NC
NC
NC
SCK
SI
.430”
PIN NAMES
Symbol
CS
SO
SI
SCK
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
No Connect
3091 FM T01
WP
V
SS
V
CC
HOLD
NC
2
X25128
PRINCIPLES OF OPERATION
The X25128 is a 8K x 8 E
2
PROM designed to inter-
face directly with the synchronous serial peripheral
interface (SPI) of many popular microcontroller fami-
lies.
The X25128 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising SCK. CS must be low and the HOLD and
WP inputs must be high during the entire operation.
The WP input is “Don’t Care” if WPEN is set “0”.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes low. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25128 into a “PAUSE” condition. After releasing
HOLD, the X25128 will resume operation from the
point when HOLD was first asserted.
Write Enable Latch
The X25128 contains a “write enable” latch. This latch
must be SET before a write operation will be
completed internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-on condition
and after the completion of a byte, page, or status
register write cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is
formatted as follows:
7
WPEN
6
X
5
X
4
X
3
BP1
2
BP0
1
WEL
0
WIP
3091 FM T02
WPEN, BP0 and BP1 are set by the WRSR instruc-
tion. WEL and WIP are read-only and automatically set
by other operations.
The Write-In-Process (WIP) bit indicates whether the
X25128 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. During a write, all other bits are set to “1”.
The Write Enable Latch (WEL) bit indicates the status
of the “write enable” latch. When set to a “1”, the latch
is set, when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allows the user to select one of four levels of
protection. The X25128 is divided into four 32,768-bit
segments. One, two, or all four of the segments may
be protected. That is, the user may read the segments
but will be unable to alter (write) data within the
selected segments. The partitioning is controlled as
illustrated below.
Status Register Bits
BP1
0
0
1
1
BP0
0
1
0
1
Array Addresses
Protected
None
$3000–$3FFF
$2000–$3FFF
$0000–$3FFF
3091 PGM T03
Table 1. Instruction Set
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Instruction Format*
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
Write Status Register
Read Data from Memory Array beginning at selected address
Write Data to Memory Array beginning at Selected Address
(1 to 32 Bytes)
3091 PGM T04
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3
X25128
Write-Protect Enable
The Write-Protect-Enable (WPEN) is available for the
X25128 as a nonvolatile enable bit for the WP pin.
Protected Unprotected Status
WPEN WP WEL Blocks
Blocks
Register
0
0
1
1
X
X
X
X
Low
Low
High
High
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Protected
Protected
Writable
3091 PGM T05.1
indefinitely. The read operation is terminated by taking
CS high. Refer to the read E
2
PROM array operation
sequence illustrated in Figure 1.
To read the status register the CS line is first pulled
low to select the device followed by the 8-bit instruc-
tion. After the RDSR opcode is sent, the contents of
the status register are shifted out on the SO line. The
read status register sequence is illustrated in Figure 2.
Write Sequence
Prior to any attempt to write data into the X25128, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken low,
then the WREN instruction is clocked into the X25128.
After all eight bits of the instruction are transmitted, CS
must then be taken high. If the user continues the write
operation without taking CS high after issuing the
WREN instruction, the write operation will be ignored.
To write data to the E
2
PROM memory array, the user
issues the write instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go low and remain
low for the duration of the operation. The host may
continue to write up to 32 bytes of data to the X25128.
The only restriction is the 32 bytes must reside on the
same page. If the address counter reaches the end of
the page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written.
For the write operation (byte or page write) to be
completed, CS can only be brought high after bit 0 of
data byte N is clocked in. If it is brought high at any
other time the write operation will not be completed.
Refer to Figures 4 and 5 below for a detailed illustra-
tion of the write sequences and time frames in which
CS going high are valid.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5
and 6 must be “0”. This sequence is shown in Figure 6.
While the write is in progress, following a status
register or E
2
PROM write sequence, the status
register may be read to check the WIP bit. During this
time the WIP bit will be high.
Hold Operation
The HOLD input should be high (at V
IH
) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled low to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register
control the programmable hardware write protect
feature. Hardware write protection is enabled when
WP pin is low, and the WPEN bit is “1”. Hardware write
protection is disabled when either the WP pin is high
or the WPEN bit is “0”. When the chip is hardware
write protected, nonvolatile writes are disabled to the
Status Register, including the Block Protect bits and
the WPEN bit itself, as well as the block-protected
sections in the memory array. Only the sections of the
memory array that are not block-protected can be
written.
Note:
Since the WPEN bit is write protected, it
cannot be changed back to a “0”, as long as
the WP pin is held low.
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the E
2
PROM array, CS is first
pulled low to select the device. The 8-bit read instruc-
tion is transmitted to the X25128, followed by the
16-bit address of which the last 14 are used. After the
read opcode and address are sent, the data stored in
the memory at the selected address is shifted out on
the SO line. The data stored in memory at the next
address can be read sequentially by continuing to
provide clock pulses. The address is automatically
incremented to the next higher address after each byte
of data is shifted out. When the highest address is
reached ($3FFF) the address counter rolls over to
address $0000 allowing the read cycle to be continued
4
X25128
be low when HOLD is first pulled low and SCK must
also be low when HOLD is released.
The HOLD input may be tied high either directly to V
CC
or tied to V
CC
through a resistor.
Operational Notes
The X25128 powers-up in the following state:
• The device is in the low power standby state.
• A high to low transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Figure 1. Read E
2
PROM Array Operation Sequence
CS
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
• CS must come high at the proper clock count in
order to start a write cycle.
0
SCK
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
INSTRUCTION
SI
16 BIT ADDRESS
15 14 13
3
2
1
0
DATA OUT
HIGH IMPEDANCE
SO
7
MSB
6
5
4
3
2
1
0
3091 FM F03
Figure 2. Read Status Register Operation Sequence
CS
0
SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
SO
7
MSB
6
5
4
3
2
1
0
3091 FM F04
5
京公网安备 11010802033920号
EEWORLD
