This X24C08 device has been acquired by IC
MICROSYSTEMS from Xicor, Inc.
8K
ICmic
IC MICROSYSTEMS
TM
X24C08
Serial E PROM
2
1024 x 8 Bit
TYPICAL FEATURES
DESCRIPTION
The X24C08 is a CMOS 8,192 bit serial E PROM,
internally organized 1024 x 8. The X24C08 features a
serial interface and software protocol allowing operation on a
simple two wire bus.
The X24C08 is fabricated with Xicor’s advanced CMOS
Textured Poly Floating Gate Technology.
The X24C08 utilizes Xicor’s proprietary Direct Write™ cell
providing a minimum endurance of 100,000 cycles
2
•
2.7V to 5.5V Power Supply
•
Low Power CMOS
—Active Read Current Less Than 1 mA
—Active Write Current Less Than 3 mA
—Standby Current Less Than 50
∝
A
•
Internally Organized 1024 x 8
•
2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
•
Sixteen Byte Page Write Mode
—Minimizes Total Write Time Per Byte
•
Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
•
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
and a minimum data retention of 100 years.
•
8 Pin Mini-DlP, 8 Pin SOIC and 14 Pin
SOIC Packages
FUNCTIONAL DIAGRAM
(8) V
CC
(4) V
SS
(7) TEST
START CYCLE
START
STOP
H.V. GENERATION
TIMING
& CONTROL
(5) SDA
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
(6) SCL
(3) A2
(2) A1
(1) A0
+COMPARATOR
LOAD
INC
XDEC
E PROM
64 X 128
2
WORD
ADDRESS
COUNTER
R/W
YDEC
8
CK
PIN
DATA REGISTER
D
OUT
D
OUT
ACK
3842 FHD F01
© Xicor, 1991 Patents Pending
3842-1
1
Characteristics subject to change without notice
X24C08
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-Up
PIN CONFIGURATION
SOIC
NC
A
0
A
1
1
2
3
4
5
6
7
14
13
12
X24C08 11
10
9
8
NC
V
CC
TEST
NC
NC
A
2
V
SS
SCL
SDA
NC
3842 FHD F03
NC
Resistor selection graph at the end of this data sheet.
Address (A
0
, A
1
)
A
0
and A
1
are unused by the X24C08; however, they must
be tied to V
SS
to insure proper device operation.
Address (A
2
)
The A
2
input is used to set the appropriate bit of the seven bit
slave address. This input can be used static or
actively driven. If used statically, it must be tied to V
SS
or
V
CC
as appropriate. If actively driven, it must be driven
DIP/SOIC
1
2
3
4
X24C08
8
7
6
5
A
0
A
1
A
2
V
SS
V
CC
TEST
SCL
SDA
3842 FHD F02
to V
SS
or to V
CC
.
PIN NAMES
Symbol
A
0
–A
2
SDA
SCL
TEST
V
SS
V
CC
NC
Description
Address Inputs
Serial Data
Serial Clock
Hold at V
SS
Ground
Supply Voltage
No Connect
3842 PGM T01
2
X24C08
DEVICE OPERATION
The X24C08 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers, and provide
the clock for both transmit and receive operations.
Therefore, the X24C08 will be considered a slave in all
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C08 continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met.
Stop Condition
All communications must be terminated by a stop condition
which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used by the X24C08
to place the device into the standby power
mode after a read sequence. A stop condition can only be
issued after the transmitting device has released the
applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions. Refer to
Figures 1 and 2.
bus.
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
3842 FHD F06
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
3842 FHD F07
3
X24C08
lected, the X24C08 will respond with an acknowledge after
the receipt of each subsequent eight bit word.
In the read mode the X24C08 will transmit eight bits of data,
release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the X24C08
will continue to transmit data. If an acknowledge is not
detected, the X24C08 will terminate further data trans-
missions. The master must then issue a stop condition to
return the X24C08 to the standby power mode and
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device will
release the bus after transmitting eight bits. During the ninth
clock cycle the receiver will pull the SDA line LOW
to acknowledge that it received the eight bits of data.
Refer to Figure 3.
The X24C08 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been se-
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
3842 FHD F08
4
X24C08
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (see Figure 4). For the X24C08 this is fixed as
The last bit of the slave address defines the operation to be
performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the X24C08 monitors the
SDA bus comparing the slave address being transmit-
ted with its slave address (device type and state of A
2
input.) Upon a correct compare the X24C08 outputs an
acknowledge on the SDA line. Depending on the state of
the R/W bit, the X24C08 will execute a read or write
1010[B].
Figure 4. Slave Address
DEVICE TYPE
IDENTIFIER
1
0
1
0
HIGH
ORDER
WORD
ADDRESS
operation.
WRITE OPERATIONS
A2
A1
A0
R/W
DEVICE
ADDRESS
Byte Write
For a write operation, the X24C08 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
1024 words in the array. Upon receipt of the word
address the X24C08 responds with an acknowledge, and
awaits the next eight bits of data, again responding
with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
X24C08 begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress the
X24C08 inputs are disabled, and the device will not
respond to any requests from the master. Refer to
Figure 5 for the address, acknowledge and data transfer
sequence.
3842 FHD F09
The next bit addresses a particular device. A system could
have up to two X24C08 devices on the bus (see
Figure 10). The two addresses are defined by the state of
the A2 input.
The next two bits of the slave address field are an
extension of the array’s address and are concatenated
with the eight bits of address in the word address field,
providing direct access to the whole 1024 x 8 array.
Figure 5. Byte Write
S
T
BUS ACTIVITY:
MASTER
A
R
SLAVE
ADDRESS
WORD
ADDRESS
DATA
S
T
O
P
T
S
A
C
A
C
A
C
SDA LINE
BUS ACTIVITY:
X24C08
P
K
K
K
3842 FHD F10
5
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