This X24C04 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
ICmic
IC MICROSYSTEMS
TM
4K
X24C04
Serial E PROM
2
512 x 8 Bit
FEATURES
DESCRIPTION
The X24C04 is a CMOS 4096 bit serial E PROM,
internally organized 512 x 8. The X24C04 features a
serial interface and software protocol allowing
operation on a simple two wire bus.
The X24C04 is fabricated with Xicor’s advanced
CMOS Textured Poly Floating Gate Technology.
The X24C04 utilizes Xicor’s proprietary DirectWrite™
cell providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
2
•
2.7V to 5.5V Power Supply
•
Low Power CMOS
—Active Read Current Less Than 1 mA
—Active Write Current Less Than 3 mA
•
Internally Organized 512 x 8
•
2 Wire Serial Interface
—Standby Current Less Than 50
∝
A
—Bidirectional Data Transfer Protocol
•
Sixteen Byte Page Write Mode
—Minimizes Total Write Time Per Byte
•
Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
•
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
•
8 Pin Mini-DIP, 8 Pin SOIC and 14 Pin SOIC
Packages
FUNCTIONAL DIAGRAM
(8) V
CC
(4) V
SS
(7) TEST
START CYCLE
H.V. GENERATION
TIMING
& CONTROL
(5) SDA
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
(6) SCL
(3) A 2
(2) A 1
(1) A 0
+COMPARATOR
LOAD
INC
XDEC
E PROM
32 X 128
2
WORD
ADDRESS
COUNTER
R/W
YDEC
8
CK
PIN
DATA REGISTER
D
OUT
D
OUT
ACK
3839 FHD F01
DirectWrite™ is a trademark of Xicor, Inc.
© Xicor, 1991 Patents Pending
3839-1
1
Characteristics subject to change without notice
X24C04
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-Up
A
0
A
1
A
2
PIN CONFIGURATION
DIP/SOIC
1
2
3
4
X24C04
8
7
6
5
V
CC
TEST
SCL
V
SS
SDA
3839 FHD F02
Resistor selection graph at the end of this data sheet.
Address (A
0
)
A
0
is unused by the X24C04, however, it must be tied to V
SS
to insure proper device operation.
Address (A
1
, A
2
)
The Address inputs are used to set the appropriate bits of
the seven bit slave address. These inputs can be used
static or actively driven. If used statically they must be
V
SS
or V
CC
as appropriate. If driven they must be
tied to
NC
A
0
A
1
SOIC
1
2
3
4
5
6
7
14
13
12
X24C04 11
10
9
8
NC
V
CC
TEST
NC
NC
A
2
V
SS
SCL
SDA
NC
3839 FHD F03
NC
driven to V
SS
or to V
CC
.
PIN NAMES
Symbol
A
0
–A
2
SDA
SCL
TEST
V
SS
V
CC
NC
Description
Address Inputs
Serial Data
Serial Clock
Hold at V
SS
Ground
Supply Voltage
No Connect
3839 PGM T01
2
X24C04
DEVICE OPERATION
The X24C04 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers, and provide
the clock for both transmit and receive operations.
Therefore, the X24C04 will be considered a slave in all
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions. Refer to
Figures 1 and 2.
Start Condition
All command are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C04 continuously monitors the SDA and SCL
lines for the start condition and will not respond to
applications.
any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
3839 FHD F06
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
3839 FHD F07
3
X24C04
The X24C04 will respond with an acknowledge after
recognition of a start condition and its slave address.
If the device and a write operation have been selected, the
X24C04 will respond with an acknowledge after the
receipt of each subsequent eight bit word.
In the read mode the X24C04 will transmit eight bits of data,
release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the X24C04
will continue to transmit data. If an acknowledge is not
detected, the X24C04 will terminate further data transmissions
The master must then issue a stop condition to return the
X24C04 to the standby power mode and place the device
Stop Condition
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when SCL
is HIGH. The stop condition is also used by the X24C04 to
place the device in the standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received the
eight bits of data. Refer to Figure 3.
into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
3839 FHD F08
4
X24C04
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave are the device type identifier (see
Figure 4). For the X24C04 this is fixed as 1010[B].
The last bit of the slave address defines the operation to be
performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the X24C04 monitors the
SDA bus comparing the slave address being transmitted
with its slave address (device type and state of A
1
and A
2
inputs). Upon a correct compare the X24C04
outputs an acknowledge on the SDA line. Depending on the
state of the R/W bit, the X24C04 will execute a read
Figure 4. Slave Address
HIGH
ORDER
DEVICE
WORD
ADDRESS ADDRESS
DEVICE TYPE
IDENTIFIER
or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24C04 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of the
512 words of memory. Upon receipt of the word address
the X24C04 responds with an acknowledge, and awaits the
next eight bits of data, again responding with an
acknowledge. The master then terminates the transfer by
generating a stop condition, at which time the X24C04
begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress the X24C04
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.
1
0
1
0
A2
A1
A0
R/W
3839 FHD F09
The next two significant bits address a particular device. A
system could have up to four X24C04 devices on the
bus (see Figure 10). The four addresses are defined by the
state of the A
1
and A
2
inputs.
The next bit of the slave address is an extension of the
array’s address and is concatenated with the eight bits
of address in the word address field, providing direct access
to the whole 512 x 8 array.
Figure 5. Byte Write
S
T
BUS ACTIVITY:
MASTER
A
R
SLAVE
ADDRESS
WORD
ADDRESS
DATA
S
T
O
P
T
S
A
C
A
C
A
C
SDA LINE
BUS ACTIVITY:
X24C04
P
K
K
K
3839 FHD F10
5
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