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WS128K32N-55G2TCEA

Description
128Kx32 SRAM MULTICHIP PACKAGE, RADIATION TOLLERANT
Categorystorage    storage   
File Size323KB，6 Pages
ManufacturerWhite Electronic Designs Corporation
Websitehttp://www.wedc.com/
Download Datasheet Parametric View All

WS128K32N-55G2TCEA Overview

128Kx32 SRAM MULTICHIP PACKAGE, RADIATION TOLLERANT

WS128K32N-55G2TCEA Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerWhite Electronic Designs Corporation
package instruction22.4 X 22.4 MM, CERAMIC, QFP-68
Reach Compliance Codeunknown
Maximum access time55 ns
JESD-30 codeS-CQFP-G68
length22.36 mm
memory density4194304 bit
Memory IC TypeSRAM MODULE
memory width32
Number of functions1
Number of terminals68
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX32
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQFP
Package shapeSQUARE
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width22.36 mm

WS128K32N-55G2TCEA Preview

White Electronic Designs
WS128K32-XG2TXE
ADVANCED*
128Kx32 SRAM MULTICHIP PACKAGE, RADIATION TOLLERANT
FEATURES
Access Times of 35, 45, 55ns
Packaging
• 68 lead, 22.4mm CQFP (G2T), 4.57mm (0.180"),
(Package 509)
Organized as 128Kx32; User Configurable as
256Kx16 or 512Kx8
Low Power Data Retention
Commercial, Industrial and Military Temperature
Ranges
5V Power Supply
Low Power CMOS
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
TTL Compatible Inputs and Outputs
Built in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight
WS128K32-XG2TXE – 8 grams typical
Radiation tolerant with epitaxial layer on die.
6T memory cells provide excellent protection
against soft errors
FIGURE 1 – PIN CONFIGURATION FOR WS128K32N-XG2TXE
Top View
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
#
GND
CS
4
#
WE
1
#
A
6
A
7
A
8
A
9
A
10
V
CC
Pin Description
I/O
0-31
A
0-16
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
3 2 1 68 67 66 65 64 63 62 61
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
The White 68 lead G2T CQFP fills
the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC.
But the G2T has the TCE and lead
inspection advantage of the CQFP
form.
OE#
A
0-16
Block Diagram
WE
1
# CS
1
#
WE
2
# CS
2
#
WE
3
# CS
3
#
WE
4
# CS
4
#
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
#
OE#
CS
2
#
NC
WE
2
#
WE
3
#
WE
4
#
NC
NC
NC
128K x 8
128K x 8
128K x 8
128K x 8
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
December 2000
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
Min
-55
-65
-0.5
-0.5
Max
+125
+150
V
CC
+0.5
150
7.0
Unit
°C
°C
V
°C
V
CS#
H
L
L
L
OE#
X
L
X
H
WE#
X
H
L
H
WS128K32-XG2TXE
ADVANCED
TRUTH TABLE
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Opertating Temp. (MIL)
Symbol
V
CC
V
IH
V
IL
T
A
Min
4.5
2.2
-0.3
-55
Max
5.5
V
CC
+ 0.3
+0.8
+125
Unit
V
V
V
°C
CAPACITANCE
T
A
= +25°C
Parameter
OE# capacitance
WE
1-4
# capacitance
CQFP G2T
CS
1-4
# capacitance
Data# I/O capacitance
Address input capacitance
Symbol
Conditions
C
OE
V
IN
= 0V, f = 1.0 MHz
C
WE
V
IN
= 0V, f = 1.0 MHz
C
CS
C
I/O
C
AD
Max Unit
50 pF
pF
20
V
IN
= 0V, f = 1.0 MHz 20 pF
V
I/O
= 0V, f = 1.0 MHz 20 pF
V
IN
= 0V, f = 1.0 MHz 50 pF
RADIATION CHARACTERISTICS
Total Dose
(TM1019.5)
Functional
(Krads)
30
Parametric
(Krads)
30
Latch-up
25°C
V
CC
Max
This parameter is guaranteed by design but not tested.
SEU LET
Threshold
(V
CC
MIN)
Cross
Section
/BIT
(E-6 cm2)
Typical Iccsb (mA
)
(MeV/mg/cm2) (MeV/mg/cm2)
1.2
>100
2
0.2
DC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
Sym
I
LI
I
LO
I
CC
I
SB
V
OL
V
OH
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
I
OL
= 8mA, V
CC
= 4.5
I
OH
= -40mA, V
CC
= 4.5
Min
Max
10
10
520
8
0.4
Units
µA
µA
mA
mA
V
V
2.4
DATA RETENTION CHARACTERISTICS
-55°C
≤
T
A
≤
+125°C
Characteristic
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time (1)
Operation Recovery Time (1)
NOTE: Parameter guaranteed, but not tested.
December 2000
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
Sym
V
CC
I
CCDR
T
CDR
T
R
Conditions
V
CC
= 2.0V
CS ≥ V
CC
-0.2V
V
IN
≥ V
CC
-0.2V
or V
IN
≤ 0.2V
Min
2
—
0
T
RC
Max
—
1
—
—
Units
V
mA
ns
ns
White Electronic Designs
AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
t
OLZ
1
t
CHZ
1
t
OHZ
1
Min
35
3
35
15
3
0
20
12
3
0
20
15
-35
Max
35
3
45
20
Min
45
-45
Max
45
WS128K32-XG2TXE
ADVANCED
-55
Min
55
3
55
30
3
0
20
20
Max
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
t
WHZ
1
t
DH
Min
35
25
25
20
25
0
0
0
0
-35
Max
Min
45
35
35
25
35
0
0
0
0
-45
Max
Min
55
45
45
25
45
0
0
0
0
-55
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
10
15
20
1. This parameter is guaranteed by design but not tested.
FIGURE 2 – AC TEST CIRCUIT
AC Test Conditions
I
OL
Current Source
D.U.T.
C
eff
= 50 pf
V
Z
1.5V
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
(Bipolar Supply)
I
OH
Current Source
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
December 2000
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WS128K32-XG2TXE
ADVANCED
FIGURE 3 – TIMING WAVEFORM - READ CYCLE
CS#
OE#
READ CYCLE 1, (CS# = OE# = V
IL
, WE# = V
IH
)
READ CYCLE 2 (WE# = V
IH
)
FIGURE 4 – WRITE CYCLE - WE# CONTROLLED
CS#
WE#
WRITE CYCLE 1, WE# CONTROLLED
FIGURE 5 – WRITE CYCLE - CS# CONTROLLED
WS32K32-XHX
CS#
WE#
WRITE CYCLE 2, CS# CONTROLLED
December 2000
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WS128K32-XG2TXE
ADVANCED
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
25.15 (0.990) ± 0.26 (0.010) SQ
22.36 (0.880) ± 0.26 (0.010) SQ
4.57 (0.180) MAX
0.27 (0.011) ± 0.04 (0.002)
Pin 1
0.25 (0.010) REF
24.03 (0.946)
± 0.26 (0.010)
1° / 7°
1.0 (0.040)
± 0.127 (0.005)
R 0.25
(0.010)
0.19 (0.007)
± 0.06 (0.002)
23.87
(0.940) REF
DETAIL A
1.27
(0.050)
TYP
SEE DETAIL "A"
0.38 (0.015) ± 0.05 (0.002)
20.3 (0.800) REF
The White 68 lead G2T CQFP
fills the same fit and function
as the JEDEC 68 lead CQFJ
or 68 PLCC. But the G2T has
the TCE and lead inspection
advantage of the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
December 2000
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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