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SI5330M-B00231-GM

Description
IC CLK BUFFER 1:4 HCSL 24QFN
Categorylogic    logic   
File Size525KB,20 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
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SI5330M-B00231-GM Overview

IC CLK BUFFER 1:4 HCSL 24QFN

SI5330M-B00231-GM Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Parts packaging codeQFN
package instructionQFN-24
Contacts24
Reach Compliance Codecompliant
series5330
Input adjustmentSTANDARD
JESD-30 codeS-XQCC-N24
length4 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level3
Number of functions1
Number of inverted outputs
Number of terminals24
Actual output times4
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)4 ns
Same Edge Skew-Max(tskwd)0.1 ns
Maximum seat height0.9 mm
Maximum supply voltage (Vsup)3.63 V
Minimum supply voltage (Vsup)2.97 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width4 mm
Base Number Matches1
S i533 0
1 . 8/ 2 .5 /3 .3 V L
O W
-J
I T T E R
, L
O W
-S
K E W
C
L O C K
B
U F F E R
/L
E V E L
T
R A N S L A T O R
Features
Supports single-ended or
differential input clock signals
Generates four differential
(LVPECL, LVDS, HCSL) or eight
single-ended (CMOS, SSTL,
HSTL) outputs
Provides signal level translation

Differential to single-ended

Single-ended to differential

Differential to differential

Single-ended to single-ended
Wide frequency range

LVPECL, LVDS: 5 to 710 MHz

HCSL: 5 to 250 MHz

SSTL, HSTL: 5 to 350 MHz

CMOS: 5 to 200 MHz
Additive jitter: 150 fs RMS typ
Output-output skew: 100 ps
Propagation delay: 2.5 ns typ
Single core supply with excellent
PSRR: 1.8, 2.5, or 3.3 V
Output driver supply voltage
independent of core supply: 1.5,
1.8, 2.5, or 3.3 V
Loss of Signal (LOS) indicator
allows system clock monitoring
Output Enable (OEB) pin allows
glitchless control of output clocks
Low power: 10 mA typical core
current
Industrial temperature range:
–40 to +85
°
C
Small size: 24-lead, 4 x 4 mm
QFN
Ordering Information:
See page 14.
Pin Assignments
Applications
High Speed Clock Distribution
Ethernet Switch/Router
SONET / SDH
PCI Express 2.0/3.0
Fibre Channel
MSAN/DSLAM/PON
Telecom Line Cards
Functional Block Diagram
Rev. 1.2 4/17
Copyright © 2017 by Silicon Laboratories
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