STM32L452VCI6 datasheet, PDF - EEWORLD Datasheet

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STM32L452VCI6: DescriptionIC MCU 32BIT 256KB FLASH 100UFBG; CategoryThe embedded processor and controller Microcontrollers and processors; File Size15MB，1600 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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STM32L452VCI6 Overview

IC MCU 32BIT 256KB FLASH 100UFBG

STM32L452VCI6 Parametric

Parameter Name	Attribute value
Brand Name	STMicroelectronics
Maker	STMicroelectronics
package instruction	VFBGA,
Reach Compliance Code	compliant
Factory Lead Time	14 weeks
Has ADC	YES
Address bus width
bit size	32
maximum clock frequency	48 MHz
DMA channel	YES
External data bus width	8
length	7 mm
Number of I/O lines	83
Number of terminals	100
PWM channel	YES
encapsulated code	VFBGA
Package shape	SQUARE
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
speed	80 MHz
Maximum supply voltage	3.6 V
Minimum supply voltage	1.71 V
Nominal supply voltage	3 V
surface mount	YES
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC
Base Number Matches	1

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RM0394

Reference manual

STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx

advanced Arm

-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx microcontroller memory and

peripherals.

The STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx is a family of microcontrollers with

different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

corresponding datasheets.

For information on the Arm

Cortex

-M4 core, please refer to the Cortex

-M4 Technical

Reference Manual.

Related documents

•

Cortex

-M4 Technical Reference Manual, available from: http://infocenter.arm.com

•

STM32L412xx, STM32L422xx, STM32L431xx, STM32L432xx, STM32L433xx,

STM32L442xx, STM32L443xx, STM32L451xx, STM32L452xx, STM32L462xx

datasheets

•

STM32F3, STM32F4, STM32L4 and STM32L4+ Series Cortex

-M4 (PM0214)

October 2018

RM0394 Rev 4

1/1600

www.st.com

Contents

RM0394

Contents

Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

1.1

1.2

1.3

1.4

1.5

General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Product specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.1

System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.1.1

2.1.2

2.1.3

2.1.4

2.1.5

S0: I-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

S1: D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

S2: S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

S3, S4: DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 67

2.2

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

2.2.1

2.2.2

2.3

2.4

Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

2.4.1

2.4.2

2.4.3

2.4.4

SRAM2 parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

SRAM2 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

SRAM2 Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

SRAM2 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

2.5

2.6

Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Embedded Flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.1

3.2

3.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.3.1

3.3.2

3.3.3

Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Read access latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

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3.3.4

3.3.5

3.3.6

3.3.7

Contents

Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 80

Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Flash main memory erase sequences

. . . . . . . . . . . . . . . . . . . . . . . . . . 83

Flash main memory programming sequences . . . . . . . . . . . . . . . . . . . . 84

Option bytes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Option bytes programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Proprietary code readout protection (PCROP) . . . . . . . . . . . . . . . . . . . 97

Write protection (WRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

3.4

FLASH option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.4.1

3.4.2

3.5

FLASH memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.5.1

3.5.2

3.5.3

3.6

3.7

FLASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

3.7.1

3.7.2

3.7.3

3.7.4

3.7.5

3.7.6

3.7.7

3.7.8

3.7.9

3.7.10

3.7.11

3.7.12

3.7.13

Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . 100

Flash Power-down key register (FLASH_PDKEYR) . . . . . . . . . . . . . . 101

Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . 102

Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Flash ECC register (FLASH_ECCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Flash option register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . . 107

Flash PCROP Start address register (FLASH_PCROP1SR) . . . . . . . 109

Flash PCROP End address register (FLASH_PCROP1ER) . . . . . . . . 109

Flash WRP area A address register (FLASH_WRP1AR) . . . . . . . . . . 110

Flash WRP area B address register (FLASH_WRP1BR) . . . . . . . . . . 110

FLASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Firewall (FW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

4.1

4.2

4.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Firewall main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Firewall functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

Firewall AMBA bus snoop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Functional requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Firewall segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Segment accesses and properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Firewall initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

RM0394 Rev 4

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Contents

4.3.6

RM0394

Firewall states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Code segment start address (FW_CSSA) . . . . . . . . . . . . . . . . . . . . . . 121

Code segment length (FW_CSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Non-volatile data segment start address (FW_NVDSSA) . . . . . . . . . . 122

Non-volatile data segment length (FW_NVDSL) . . . . . . . . . . . . . . . . . 122

Volatile data segment start address (FW_VDSSA) . . . . . . . . . . . . . . . 123

Volatile data segment length (FW_VDSL) . . . . . . . . . . . . . . . . . . . . . . 123

Configuration register (FW_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Firewall register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4.4

Firewall registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

4.4.1

4.4.2

4.4.3

4.4.4

4.4.5

4.4.6

4.4.7

4.4.8

Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

5.1

Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Independent analog peripherals supply . . . . . . . . . . . . . . . . . . . . . . . . 128

Independent USB transceivers supply . . . . . . . . . . . . . . . . . . . . . . . . . 129

Independent LCD supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

VDD12 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . 133

Power-on reset (POR) / power-down reset (PDR) / brown-out reset

(BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 135

Peripheral Voltage Monitoring (PVM) . . . . . . . . . . . . . . . . . . . . . . . . . 136

Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Low-power run mode (LP run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Low-power sleep mode (LP sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Auto-wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . 157

5.2

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

5.2.1

5.2.2

5.2.3

5.3

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

5.3.10

5.3.11

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RM0394 Rev 4

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Contents

5.4

PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

5.4.6

5.4.7

5.4.8

5.4.9

5.4.10

5.4.11

5.4.12

5.4.13

5.4.14

5.4.15

5.4.16

5.4.17

5.4.18

5.4.19

5.4.20

Power control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 158

Power control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 159

Power control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . 160

Power control register 4 (PWR_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . 161

Power status register 1 (PWR_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Power status register 2 (PWR_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Power status clear register (PWR_SCR) . . . . . . . . . . . . . . . . . . . . . . . 165

Power Port A pull-up control register (PWR_PUCRA) . . . . . . . . . . . . . 166

Power Port A pull-down control register (PWR_PDCRA) . . . . . . . . . . 166

Power Port B pull-up control register (PWR_PUCRB) . . . . . . . . . . . . . 167

Power Port B pull-down control register (PWR_PDCRB) . . . . . . . . . . 167

Power Port C pull-up control register (PWR_PUCRC) . . . . . . . . . . . . 168

Power Port C pull-down control register (PWR_PDCRC) . . . . . . . . . . 168

Power Port D pull-up control register (PWR_PUCRD) . . . . . . . . . . . . 169

Power Port D pull-down control register (PWR_PDCRD) . . . . . . . . . . 169

Power Port E pull-up control register (PWR_PUCRE) . . . . . . . . . . . . . 170

Power Port E pull-down control register (PWR_PDCRE) . . . . . . . . . . 170

Power Port H pull-up control register (PWR_PUCRH) . . . . . . . . . . . . 171

Power Port H pull-down control register (PWR_PDCRH) . . . . . . . . . . 171

PWR register map and reset value table . . . . . . . . . . . . . . . . . . . . . . . 173

Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

6.1

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

6.1.1

6.1.2

6.1.3

Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

HSI48 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Clock source frequency versus voltage scaling . . . . . . . . . . . . . . . . . . 186

6.2

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

6.2.8

6.2.9

RM0394 Rev 4

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Supplying superior products: Freescale Power Architecture processor chips: Shenzhen Longline Technology Development Co., Ltd. is an electronic product supplier specializing in the development and design, solution promotion, manufacturing and component distribution of single-...; marchz Embedded System

LM3S811 uart interrupt problem: The UART interrupt I wrote with lm3s811 can only be triggered once! It must be reset once each time before it can be triggered once! What is the reason? ? The code is as follows: #include #include #in...; zwj123zwj Microcontroller MCU

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