UM10751
OM13488 8-bit GPIO Daughter Card User Manual
Rev. 1.0 — 11 October 2013
User manual
Document information
Info
Content
Keywords
Abstract
Fm+ Development Kit, OM13320, GPIO, OM13303
Installation guide and User Manual for the OM13488 8-bit GPIO Daughter
Card that connects to OM13320 Fm+ Development Kit. This board
2
permits easy and simple evaluation of most of NXP’s 8-bit I C GPIO
portfolio of products.
NXP Semiconductors
UM10751
OM13488 8-bit GPIO User Manual
Revision history
Rev
Date
1.0
20131011
Description
Initial Release
Contact information
For more information, please visit:
http://www.nxp.com
For sales office addresses, please send an email to:
salesaddresses@nxp.com
UM10751
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
User manual
Rev. 1.0 — 11 October 2013
2 of 16
NXP Semiconductors
UM10751
OM13488 8-bit GPIO User Manual
1. Introduction
The OM13488 8-bit I C GPIO Daughter Card connects to the OM13320 Fm+ Development
2
kit and permits easy evaluation of most of NXP’s 8-bit I C GPIO portfolio of products.
Table_1
lists the supported devices.
The OM13488 8-bit I C GPIO Daughter Card is shipped with no GPIO device soldered to the
board. The user must purchase the device he is interested in evaluating in a TSSOP16
package (the ordering part number suffix should be “PW” and the package designation
should be SOT403-1). These leaded packages should be relatively easy to solder to the
board with a low wattage, fine tipped soldering iron.
2
2
Table 1.
Device
Devices Supported by OM13488 8-bit I C GPIO Daughter Card
Description
Orderable Part Number
2
PCA6408A
PCA8574A
PCA8574
PCA9534
PCA9538A
PCA9538
PCA9554A
PCA9554B
PCA9554C
PCA9554
PCA9670
PCA9672
PCA9674A
PCA9674
PCAL6408A
UM10751
Low-voltage, 8-bit I²C-bus and SMBus I/O
expander with interrupt output, reset, and
configuration registers
Remote 8-bit I/O expander for I²C-bus with
interrupt
Remote 8-bit I/O expander for I²C-bus with
interrupt
8-bit I
2
C-bus and SMBus low power I/O port
with interrupt
Low-voltage 8-bit I²C-bus I/O port with
interrupt and reset
8-bit I²C-bus and SMBus low power I/O port
with interrupt and reset
8-bit I²C-bus and SMBus I/O port with
interrupt
Low-voltage 8-bit I²C-bus and SMBus low
power I/O port with interrupt, weak pull-up
Low-voltage 8-bit I²C-bus and SMBus low
power I/O port with interrupt, weak pull-up
8-bit I²C-bus and SMBus I/O port with
interrupt
Remote 8-bit I/O expander for Fm+ I²C-bus
with reset
Remote 8-bit I/O expander for Fm+ I²C-bus
with interrupt and reset
Remote 8-bit I/O expander for Fm+ I²C-bus
with interrupt
Remote 8-bit I/O expander for Fm+ I²C-bus
with interrupt
Low-voltage translating, 8-bit I²C-bus/SMBus
I/O expander with interrupt output, reset,
All information provided in this document is subject to legal disclaimers.
PCA6408APW
PCA8574APW
PCA8574PW
PCA9534PW
PCA9538APW
PCA9538PW
PCA9554APW
PCA9554BPW
PCA9554CPW
PCA9554PW
PCA9670PW
PCA9672PW
PCA9674APW
PCA9674PW
PCAL6408APW
© NXP B.V. 2013. All rights reserved.
User manual
Rev. 1.0 — 11 October 2013
3 of 16
NXP Semiconductors
UM10751
OM13488 8-bit GPIO User Manual
Description
Orderable Part Number
Device
PCAL9538A
PCAL9554B
PCAL9554C
PCF8574
PCF8574A
and configuration registers
Low-voltage 8-bit I²C-bus and SMBus low
power I/O port with interrupt, reset and
Agile I/O
Low-voltage 8-bit I²C-bus/SMBus low power
I/O port with interrupt, weak pull-up and
Agile I/O
Low-voltage 8-bit I²C-bus/SMBus low power
I/O port with interrupt, weak pull-up and
Agile I/O
Remote 8-bit I/O expander for I
2
C-bus with
interrupt
Remote 8-bit I/O expander for I
2
C-bus with
interrupt
PCAL9538APW
PCAL9554BPW
PCAL9554CPW
PCF8574PW
PCF8574APW
The pin configuration of these devices varies only a bit and the different pin selections are
made via jumpers.
2. Features of the OM13488 8-bit GPIO Daughter Card
Direct connection to OM13320 Fm+ Development kit
Footprint for a TSSOP16 package, user solderable
Jumper configuration accommodates most NXP 8-bit GPIO
Flexible power supply configuration: 3.3V, 5V or external supply
Direct connection to OM13303 GPIO Target board for I/O visualization
Jumper configuration of device I C address
LED indicators for power and INT
Scope ground connection loop
2
3. Pin Configuration of 8-bit GPIO Devices
The different 8-bit GPIO devices pin configurations differ only slightly between devices. See
Fig 1 for a description of the different pinouts.
UM10751
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
User manual
Rev. 1.0 — 11 October 2013
4 of 16
NXP Semiconductors
UM10751
OM13488 8-bit GPIO User Manual
PCA(L)9554B & C
PCA8574/74A
PCA9674/74A
PCF8574/74A
PCA(L)9554B & C
PCA8574
PCA9674
PCF8574
VCC(P)
SDA
SCL
P0_7
P0_6
P0_5
P0_4
PCA(L)9538
PCA9672
PCA(L)6408
PCA(L)6408
PCA(L)9538
PCA9672
PCA9670
O
A0
A1
A2
P0_0
P0_1
P0_2
P0_3
VSS
VCC(I2C-bus )
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADDR
RESET
INT
RESET
Fig 1.
Pin Configuration 8-bit GPIO Devices
3.1 Power Supply Setup
Power supply voltages may be selected from the tester connector CN4 or the Fm+ board
CN2. If one selects Fm+ CN2, either 3.3V or 5V can be chosen. Additionally, the
PCA(L)6408 device implements two power supplies which are separately chosen, i.e. one
can be 3.3V and the other 5V for voltage level translation evaluation. Both of these power
supplies can be supplied externally by using TP1 and TP2 near the tester connector CN4.
See the schematic section at the end of this document for more details.
The jumpers for power supply selection are JP2, JP3, and JP4
3.2 Reset, Interrupt, and Address pins selection
The Reset, Interrupt and Address pins are used in combinations on various devices. The
selection matrix on the 8-bit GPIO board sends pins 2, 3, and 13 to determine if the pins are
address or function on JP9, JP10, and JP11. Then, if they are determined address pins, JP1,
JP7 and JP8 tie them to logic high or low. If they are determined to be function pins, the
other position of JP9, JP10 and JP11 tie them to the correct connector function pins. See the
schematic section at the end of this document for more details.
The logic high level for the address pins is VDDP.
UM10751
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
User manual
Rev. 1.0 — 11 October 2013
PCA9670
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