SiT5021
1-220 MHz High Performance Differential (VC) TCXO
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
Any frequency between 1 MHz and 220 MHz accurate to 6 decimal
places
LVPECL and LVDS output signaling types
0.6ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth
Frequency stability as low as ±5 ppm. Contact SiTime for tighter
stability options
Industrial and extended commercial temperature ranges
Industry-standard packages: 3.2 x 2.5, 5.0 x 3.2 and 7.0 x 5.0 mm
For frequencies higher than 220 MHz, refer to SiT5022 datasheet
SATA, SAS, 10GB Ethernet, Fibre Channel, PCI-Express
Networking, broadband, instrumentation
Electrical Characteristics
Parameter and Conditions
Supply Voltage
Symbol
Vdd
Min.
2.97
2.25
2.25
Output Frequency Range
Initial Tolerance
Stability Over Temperature
f
F_init
F_stab
-5
Supply Voltage
Output Load
First Year Aging
10-year Aging
Operating Temperature Range
Pull Range
Upper Control Voltage
Control Voltage Range
Control Voltage Input Impedance
Frequency Change Polarity
Control Voltage -3dB Bandwidth
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
Start-up Time
Resume Time
Duty Cycle
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Standby Current
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
OE Enable/Disable Time
RMS Period Jitter
F_vdd
F_load
F_aging1
F_aging10
T_use
PR
VC_U
VC_L
Z_vc
–
V_BW
VIH
VIL
Z_in
T_start
T_resume
DC
Idd
I_OE
I_leak
I_std
I_driver
VOH
VOL
V_Swing
Tr, Tf
T_oe
T_jitt
–
70%
–
–
2
–
–
45
–
–
–
–
–
Vdd-1.1
Vdd-1.9
1.2
–
–
–
–
–
RMS Phase Jitter (random)
T_phj
–
Vdd-0.1
–
100
–
–
-2.5
-5
-40
-20
–
50
0.1
–
–
–
–
±12.5, ±25, ±50
–
–
–
Positive slope
–
–
–
100
–
6
6
–
61
–
–
–
–
–
–
1.6
300
–
1.2
1.2
1.2
0.6
8
–
30%
250
–
10
10
55
69
35
1
100
30
Vdd-0.7
Vdd-1.5
2.0
500
115
1.7
1.7
1.7
0.85
–
0.1
–
+5
–
–
+2.5
+5
+85
+70
ppm
ppb
ppm
ppm
ppm
°C
°C
ppm
V
V
k
–
kHz
Vdd
Vdd
kΩ
MΩ
ms
ms
%
mA
mA
A
A
mA
V
V
V
ps
ns
ps
ps
ps
ps
Pin 1, OE or ST
Pin 1, OE or ST
Pin 1, OE logic high or logic low, or ST logic high
Pin 1, ST logic low
Measured from the time Vdd reaches its rated minimum value.
In Standby mode, measured from the time ST pin crosses
Contact SiTime for tighter duty cycle
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
ST = Low, for all Vdds
Maximum average current drawn from OUT+ or OUT-
See Figure 1(a)
See Figure 1(a)
See Figure 1(b)
20% to 80%, see Figure 1(a)
f = 212.5 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, VDD = 3.3V or 2.5V
f = 212.5 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
All Vdds. Voltage at which maximum deviation is guaranteed.
1
-2
Typ.
3.3
2.5
–
–
–
Max.
3.63
2.75
3.63
220
2
Unit
V
V
V
MHz
ppm
At 25°C after two reflows
Over operating temperature range at rated nominal power
supply voltage and load.
Contact SiTime for tighter stability options.
±10% Vdd
15 pF ±10% of load
25°C
25°C
Industrial
Extended Commercial
Termination schemes in Figures 1 and 2 - XX ordering code
Condition
LVPECL and LVDS, Common Electrical Characteristics
LVPECL, DC and AC Characteristics
SiTime Corporation
Rev. 1.5
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised November 12, 2015
SiT5021
1-220 MHz High Performance Differential (VC) TCXO
The Smart Timing Choice
The Smart Timing Choice
Electrical Characteristics
(continued)
Parameter and Conditions
Current Consumption
OE Disable Supply Current
Differential Output Voltage
Output Disable Leakage Current
Standby Current
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
Rise/Fall Time
OE Enable/Disable Time
RMS Period Jitter
Symbol
Idd
I_OE
VOD
I_leak
I_std
VOD
VOS
VOS
Tr, Tf
T_oe
T_jitt
Min.
–
–
250
–
–
–
1.125
–
–
–
–
–
–
RMS Phase Jitter (random)
T_phj
–
Typ.
47
–
350
–
–
–
1.2
–
495
–
1.2
1.2
1.2
0.6
Max.
55
35
450
1
100
50
1.375
50
600
115
1.7
1.7
1.7
0.85
Unit
mA
mA
mV
A
A
mV
V
mV
ps
ns
ps
ps
ps
ps
Condition
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
See Figure 2
OE = Low
ST = Low, for all Vdds
See Figure 2
See Figure 2
See Figure 2
20% to 80%, see Figure 2
f = 212.5 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, VDD = 3.3V or 2.5V
f = 212.5 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
LVDS, DC and AC Characteristics
Pin Description
Pin
Map
V Control
1
VC/OE/ST
Output Enable
Standby
2
3
4
5
6
NC
GND
OUT+
OUT-
VDD
NA
Power
Output
Output
Power
Voltage control
H or Open: specified frequency output
L: output is high impedance
H or Open: specified frequency output
L: Device goes to sleep mode. Supply current reduces to I_std.
No Connect; Leave it floating or connect to GND for better heat dissipation
VDD Power Supply Ground
Oscillator output
Complementary oscillator output
Power supply voltage
Functionality
Top View
VC/OE/ST
NC
GND
1
6
VDD
OUT-
OUT+
2
5
3
4
Absolute Maximum
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of
the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge (HBM)
Soldering Temperature (follow standard Pb free soldering guidelines)
Min.
-65
-0.5
–
–
Max.
150
4
2000
260
Unit
°C
V
V
°C
Thermal Consideration
Package
7050, 6-pin
5032, 6-pin
3225, 6-pin
JA, 4 Layer Board
(°C/W)
142
97
109
JC, Bottom
(°C/W)
27
20
20
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.5
Page 2 of 8
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