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8SLVP1212ANLGI/W

Description
IC CLK BUFFER LVPECL 40VFQFPN
Categorysemiconductor    Analog mixed-signal IC   
File Size781KB,25 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance
Download Datasheet Parametric View All

8SLVP1212ANLGI/W Overview

IC CLK BUFFER LVPECL 40VFQFPN

8SLVP1212ANLGI/W Parametric

Parameter NameAttribute value
typefanout buffer (allocation), multiplexer
Number of circuits1
Ratio - Input:Output2:12
Differential - Input:OutputYes Yes
enterCML,LVCMOS,LVDS,LVPECL
outputLVPECL
Frequency - maximum2GHz
Voltage - Power2.375 V ~ 3.465 V
Operating temperature-40°C ~ 85°C
Installation typesurface mount
Package/casing40-VFQFN Exposed Pad
Supplier device packaging40-VFQFPN(6x6)
Low Phase Noise, 1-to-12, 3.3V, 2.5V
LVPECL Output Fanout Buffer
General Description
The IDT8SLVP1212I is a high-performance, 12 output differential
LVPECL fanout buffer. The device is designed for the fanout of
high-frequency, very low additive phase-noise clock and data signals.
The IDT8SLVP1212I is characterized to operate from a 3.3V and
2.5V power supply. Guaranteed output-to-output and part-to-part
skew characteristics make the IDT8SLVP1212I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and twelve low skew
outputs are available. The integrated bias voltage generators enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
IDT8SLVP1212I
DATASHEET
Features
Twelve low skew, low additive jitter LVPECL outputs
Two selectable, differential clock inputs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input (input select)
Output skew: 33ps (maximum)
Propagation delay: 550ps (maximum)
Low additive phase jitter, RMS at f
REF
= 156.25MHz, V
PP
= 1V,
12kHz-20MHz: 60fs (maximum)
Full 3.3V and 2.5V supply voltage
Device current consumption (I
EE
): 131mA (maximum)
Available in Lead-free (RoHS 6), 40-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Differential PCLK0, nPCLK0 and PCLK1, nPCLK1 pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B)
Block Diagram
Q0
nQ0
Q1
nQ1
Q2
nQ2
V
CC
Pin Assignment
nQ7
nQ5
nQ6
nQ4
V
EE
30 29 28 27 26 25 24 23 22 21
V
CC
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
Q3
nQ3
Q4
nQ4
f
REF
31
32
33
34
35
36
37
38
39
V
EE
20
19
18
17
16
15
14
13
12
Q7
Q6
Q5
Q4
V
CC
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
CC
PCLK0
nPCLK0
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
V
CC
V
CC
40
SEL
PCLK1
nPCLK1
nPCLK0
PCLK0
V
CC
V
CC
SEL
Q9
nQ9
Q10
nQ10
Q11
nQ11
IDT8SLVP1212I
40-lead VFQFN
6mm x 6mm x 0.925mm package body,
2.9mm x 2.9mm E-Pad size
NL Package, Top View
V
REF
Voltage
Reference
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014
1
©2014 Integrated Device Technology, Inc.
VREF
PCLK1
nPCLK1
1
2 3 4
nc
5
6
7 8 9 10
11
nc
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