BLM2425M7S60P
LDMOS 2-stage power MMIC
Rev. 5 — 13 September 2018
Product data sheet
1. Product profile
1.1 General description
60W dual path, 2-stage power MMIC transistor for Industrial, Scientific and Medical (ISM)
applications at frequencies from 2400 MHz to 2500 MHz.
The BLM2425M7S60P is designed for high power CW applications and is assembled in a
high performance plastic package.
Table 1.
Application performance
Per section unless otherwise specified.
Test signal
CW
f
(MHz)
2450
V
DS
(V)
32
P
L
(W)
30
G
p
(dB)
27.5
η
D
(%)
45
1.2 Features and benefits
High efficiency
High power gain
Excellent ruggedness
Excellent thermal stability
Integrated ESD protection
Biasing of individual stages is externally accessible
On-chip matching for ease of use
Designed for broadband operation (frequency 2400 MHz to 2500 MHz)
For RoHS compliance see the product details on the Ampleon website
1.3 Applications
Industrial, scientific and medical applications in the frequency range 2400 MHz to
2500 MHz.
BLM2425M7S60P
LDMOS 2-stage power MMIC
2. Pinning information
2.1 Pinning
pin 1 index
V
DS(A1)
V
GS(A2)
V
GS(A2)
RF_IN_A
V
GS(A1)
V
GS(A1)
n.c.
n.c.
V
GS(B1)
V
GS(B1)
RF_IN_B
V
GS(B2)
V
GS(B2)
V
DS(B1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
RF_OUT_
V
DS(A2)
15
RF_OUT_
V
DS(B2)
amp00795
Transparent top view
The exposed backside of the package is the ground terminal of the device.
Fig 1.
Pin configuration
2.2 Pin description
Table 2.
Symbol
V
DS(A1)
V
GS(A2)
RF_IN_A
V
GS(A1)
n.c.
n.c.
V
GS(B1)
RF_IN_B
V
GS(B2)
V
DS(B1)
RF_OUT_B/V
DS(B2)
RF_OUT_A/V
DS(A2)
GND
Pin description
Pin
1
2, 3
4
5, 6
7
8
9, 10
11
14
15
16
Description
drain-source voltage of stage A1
gate-source voltage of stage A2
RF input path A
gate-source voltage of stage A1
not connected
not connected
gate-source voltage of stage B1
RF input path of B
drain-source voltage of stage B1
RF output path B / drain source voltage of stage B2
RF output path A / drain source voltage of stage A2
12, 13 gate-source voltage of stage B2
flange RF ground
BLM2425M7S60P
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2018. All rights reserved.
Product data sheet
Rev. 5 — 13 September 2018
2 of 13
BLM2425M7S60P
LDMOS 2-stage power MMIC
3. Ordering information
Table 3.
Ordering information
Package
Name Description
BLM2425M7S60P -
plastic, heatsink small outline package; 16 leads (flat)
Version
SOT1211-3
Type number
4. Block diagram
V
DS(A1)
RF_IN_A
V
GS(A1)
V
GS(A2)
V
GS(B2)
V
GS(B1)
RF_IN_B
V
DS(B1)
aaa-018263
RF_OUT_A / V
DS(A2)
RF_OUT_B / V
DS(B2)
Fig 2.
Block diagram of BLM2425M7S60P
5. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
V
GS(sense)
T
stg
T
j
T
case
[1]
Parameter
drain-source voltage
gate-source voltage
sense gate-source voltage
storage temperature
junction temperature
case temperature
Conditions
Min
-
0.5
0.5
65
[1]
Max
65
+13
+9
+150
225
150
Unit
V
V
V
C
C
C
-
-
Continuous use at maximum temperature will affect the reliability, for details refer to the online MTF
calculator.
BLM2425M7S60P
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2018. All rights reserved.
Product data sheet
Rev. 5 — 13 September 2018
3 of 13
BLM2425M7S60P
LDMOS 2-stage power MMIC
6. Thermal characteristics
Table 5.
Thermal characteristics
Measured for total device.
Symbol Parameter
R
th(j-c)
[1]
Conditions
final stage; T
case
= 90
C;
P
L
= 60 W
[1]
Value Unit
0.91
K/W
thermal resistance from
junction to case
When operated with a CW signal.
7. Characteristics
Table 6.
DC characteristics
T
case
= 25
°C;
per section unless otherwise specified.
Symbol
V
(BR)DSS
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
I
Dq
Parameter
Conditions
Min Typ
65
1.5
1.7
-
-
-
-
-
-
1.9
2.1
-
7.8
-
350
Max Unit
-
2.3
2.5
1.4
-
140
-
257
V
V
V
A
A
nA
S
m
mA
Final stage
drain-source breakdown voltage V
GS
= 0 V; I
D
= 0.422 mA
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
V
DS
= 10 V; I
D
= 42 mA
V
DS
= 28 V; I
D
= 253 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 1478 mA
2.85 -
drain-source on-state resistance V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 1.48 A
quiescent drain current
main transistor: V
DS
= 28 V
sense transistor: I
D
= 7 mA;
V
DS
= 28 V
208 233
Driver stage
V
(BR)DSS
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
I
Dq
drain-source breakdown voltage V
GS
= 0 V; I
D
= 0.116 mA
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
V
DS
= 10 V; I
D
= 11.6 mA
V
DS
= 28 V; I
D
= 69.6 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 406 mA
65
1.4
1.7
-
-
-
-
-
67
-
1.9
2.1
-
2.2
-
0.8
-
2.4
2.5
1.4
-
140
-
V
V
V
A
A
nA
S
m
mA
drain-source on-state resistance V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 0.4 A
quiescent drain current
main transistor: V
DS
= 28 V
sense transistor: I
D
= 7 mA;
V
DS
= 28 V
2350 -
75
83
BLM2425M7S60P
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2018. All rights reserved.
Product data sheet
Rev. 5 — 13 September 2018
4 of 13
BLM2425M7S60P
LDMOS 2-stage power MMIC
Table 7.
RF Characteristics
Test signal: CW at f = 2450 MHz; RF performance at V
DS
= 32 V; I
Dq1
= 25 mA; I
Dq2
= 50 mA;
T
case
= 25
°C;
per section unless otherwise specified; in a class-AB production circuit.
Symbol
G
p
D
RL
in
Parameter
power gain
drain efficiency
input return loss
Conditions
P
L
= 30 W
P
L
= 30 W
P
L
= 30 W
Min
26
41.5
-
Typ
27.5
45
18
Max
-
-
Unit
dB
%
13.8
dB
8. Test information
8.1 Ruggedness
The BLM2425M7S60P is capable of withstanding a load mismatch corresponding to
VSWR = 15 : 1 through all phases under the following conditions: V
DS
= 32 V;
I
Dq1
= 25 mA; I
Dq2
= 50 mA; f = 2450 MHz; per section unless otherwise specified.
8.2 Impedance information
Table 8.
Typical impedance
Measured load-pull data. Typical values per section unless otherwise specified.
f
(MHz)
2400
2450
2500
[1]
Z
S
[1]
(Ω)
19.1 + j43.2
16.8 + j38.8
14.4 + j33.0
Z
L
[1]
(Ω)
5.3
j2.4
5.0
j2.3
4.4
j2.4
Z
S
and Z
L
defined in
Figure 3
drain
Z
L
gate
Z
S
001aaf059
Fig 3.
Definition of transistor impedance
BLM2425M7S60P
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2018. All rights reserved.
Product data sheet
Rev. 5 — 13 September 2018
5 of 13
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