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WF4M32-100G2TI5

Description
4M X 32 FLASH 5V PROM MODULE, 100 ns, CPGA66
Categorystorage   
File Size311KB,15 Pages
ManufacturerWhite Electronic Designs Corporation
Websitehttp://www.wedc.com/
Download Datasheet Parametric View All

WF4M32-100G2TI5 Overview

4M X 32 FLASH 5V PROM MODULE, 100 ns, CPGA66

WF4M32-100G2TI5 Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals66
Maximum operating temperature125 Cel
Minimum operating temperature-55 Cel
Maximum supply/operating voltage5.5 V
Minimum supply/operating voltage4.5 V
Rated supply voltage5 V
maximum access time100 ns
Processing package description1.385 X 1.385 INCH, HERMETIC SEALED, CERAMIC, HIP-66
stateTRANSFERRED
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeGRID ARRAY
Terminal formPIN/PEG
Terminal spacing2.54 mm
terminal coatingTIN LEAD
Terminal locationPERPENDICULAR
Packaging MaterialsCERAMIC, METAL-SEALED COFIRED
Temperature levelMILITARY
memory width32
organize4M X 32
storage density1.34E8 deg
operating modeASYNCHRONOUS
Number of digits4.19E6 words
Number of digits4M
Memory IC typeFLASH 5V PROM MODULE
serial parallelPARALLEL
White Electronic Designs
FEATURES
n
n
Packaging:
• 66 pin, PGA Type, 1.385" square, Hermetic
Ceramic HIP (Package 402).
• 68 lead, 40mm Low Profile CQFP ( Package
502 ), 3.5mm (0.140") height.
• 68 lead, Hermetic CQFP (G2T), 22.4mm
(0.880") square (Package 509) 4.57mm
(0.180") height. Designed to fit JEDEC 68
lead 0.990CQFJ footprint (Fig. 3)
n
Sector Architecture
• 32 equal size sectors of 64KBytes per each
2Mx8 chip
• Any combination of sectors can be erased. Also
supports full chip erase.
n
Minimum 100,000 Write/Erase Cycles Minimum
n
Organized as 4Mx32
WF4M32-XXX5
PRELIMINARY*
4MX32 5V FLASH MODULE, SMD 5962-97612 (pending)
Access Times of 100, 120, 150ns
n
User configurable as 8Mx16 or 16Mx8 in HIP and
G4T packages.
n
Commercial, Industrial, and Military Temperature Ranges
n
5 Volt Read and Write. 5V ± 10% Supply.
n
Low Power CMOS
n
Data Polling and Toggle Bit feature for detection of
program or erase cycle completion.
n
Supports reading or programming data to a sector
not being erased.
n
RESET pin resets internal state machine to the read
mode.
n
Built-in Decoupling Caps and Multiple Ground
Pins for Low Noise Operation, Separate Power
and Ground Planes to improve noise immunity
*This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Note:
For programming information refer to Flash Programming 16M5 Application Note.
F
IG
. 1
1
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
A
18
I/O
0
I/O
1
I/O
2
11
P
IN
C
ONFIGURATION
F
OR
WF4M32-XH2X5
T
OP
V
IEW
12
RESET
P
IN
D
ESCRIPTION
I/O
0-31
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Reset
A
0-21
WE
CS
1-4
OE
23
I/O
15
I/O
14
I/O
13
I/O
12
OE
A
17
WE
I/O
7
I/O
6
I/O
5
I/O
4
33
I/O
24
I/O
25
I/O
26
A
7
A
12
A
21
A
13
A
8
I/O
16
I/O
17
I/O
18
34
V
CC
CS
4
NC
I/O
27
A
4
A
5
A
6
A20
CS
3
GND
I/O
19
44
45
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
56
CS
2
GND
I/O
11
A
10
A
9
A
15
V
CC
CS
1
A
19
I/O
3
22
V
CC
GND
RESET
B
LOCK
D
IAGRAM
CS
1
A
21
CS
2
CS
3
CS
4
I/O
23
I/O
22
OE
WE
I/O
21
I/O
20
55
66
A
0-20
RESET
2M x 8
2M x 8
2Mx 8
2M x 8
2M
x 8
2M
x 8
2M
x 8
2M
x 8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
August 2002 Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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