White Electronic Designs
128MB to 1GB Industrial ATA Flash
FEATURES
ATA Compatibility
• 3.3V or 5.0V single power supply.
• 68 pin two piece connector with Type-2 form
factor (5mm thickness)
• Support for CIS implementation with 256 bytes of
attribute memory
Interface modes
• PC card memory mode
• PC card I/O mode
• True IDE mode
High performance
• Interface Transfer speed in PIO mode 4 or Multi
Word DMA mode 2 cycle timing, 16.6 Mbytes/
second (theoretical)
• Sustained write: max 6.0 Mbytes/s in ATA PIO
mode 4 cycle timing
• Sustained read: max 6.5 Mbytes/s in ATA PIO
mode 4 cycle timing
W/E Endurance:
100,000cycles
1
/300,000cycles
2
Notes: 1. T
A
= -40 to 85°C
2. T
A
= 0 to 70°C
WED7PxxxATA70xxI25
512MB and 1.02GB unformatted capacity. Being able
to emulate IDE hard disk drives, WEDC’s ATA card is a
perfect choice for solid-state mass-storage in industrial
applications and applications that require performance
and extended environmental tolerances.
Dimensions:
Type 2 card: 85.6mm(L) x 54.0mm (W) x 5.03mm (H)
Lead free and RoHS compliant
Storage Capacities:
128MB, 256MB, 512MB and 1.02GB (unformatted)
Operating Voltage:
3.3V ± 5%
5.0V ± 0.5V
Power consumption:
• 5V operation
Active mode:
Write operation: 28 mA (Typ.)
Read operation: 23 mA (Typ.)
Power down mode: 1.2mA (Typ.) 2.0mA (max.)
• 3.3V operation
Active mode:
Write operation: 25 mA (Typ.)
Read operation: 21 mA (Typ.)
Power down mode: 1.0mA (Typ.) 1.5mA (max.)
Environment conditions:
• Operating temperature: -40°C to 85°C
• Storage temperature: -45°C to 90°C
• Storage humidity: 95% (max) (No condensation)
* This product is subject to change without notice.
DESCRIPTION
The WED7PxxxATA70xxI25 series ATA card is an ATA
interface flash memory card based on flash technology.
The ATA card is constructed with a flash disk controller
chip and NAND-type flash memory device. Operates
from a single 5-Volt or 3.3-Volt power source. The card is
available in ATA type-2 form factor with 128MB, 256MB,
PRODUCT TYPES
Card Density
128MB
256MB
512MB
1.02GB
Model No.
7P128ATA70xxI25
7P256ATA70xxI25
7P512ATA70xxI25
7P1G0ATA70xxI25
Cylinder
978
978
993
1985
Head
8
16
16
16
Sector
32
32
63
63
Memory capacity
1
128,188,416 Byte
256,376,832 Byte
512,483,328 Byte
1024,450,560 Byte
1: It is the logical address capacity including the area used for File System.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED7PxxxATA70xxI25
PIN ASSIGNMENTS AND PIN TYPE
Memory card mode
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal Name
GND
D3
D4
D5
D6
D7
CE1#
A10
OE#
N.C.
A9
A8
N.C.
N.C.
WE#
RDY/BSY
Vcc
N.C.
N.C.
N.C.
N.C.
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
WP
GND
–
–
–
–
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
–
I/O
I/O
I/O
I/O
I/O
I
I
I
–
I
I
–
–
I
O
I/O
I/O Card Mode
Signal Name
GND
D3
D4
D5
D6
D7
CE1#
A10
OE#
N.C.
A9
A8
N.C.
N.C.
WE#
IREQ#
Vcc
N.C.
N.C.
N.C.
N.C.
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
IOIS16#
GND
–
–
–
–
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
–
I/O
I/O
I/O
I/O
I/O
I
I
I
–
I
I
–
–
I
O
I/O
True IDE Mode
Signal Name
GND
D3
D4
D5
D6
D7
CE1#
A10
ATASEL#
N.C.
A9
A8
N.C.
N.C.
WE#
INTRQ
Vcc
N.C.
N.C.
N.C.
N.C.
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
IOIS16#
GND
–
–
–
–
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
–
I/O
I/O
I/O
I/O
I/O
I
I
I
–
I
I
–
–
I
O
I/O
Pin #
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Memory card mode
Signal Name
GND
CD1#
D11
D12
D13
D14
D15
CE2#
VS1
IORD#
IOWR#
NC
NC
NC
NC
NC
Vcc
NC
NC
NC
NC
CSEL#
VS2
RESET
Wait#
INPACK#
REG#
BVD2
BVD1
D8
D9
D10
CD2#
GND
I/O
–
O
I/O
I/O
I/O
I/O
I
I
O
I
I
–
–
–
–
–
–
–
–
–
–
I
O
I
O
O
I
I/O
I/O
I/O
I/O
O
O
–
I/O Card Mode
Signal Name
GND
CD1#
D11
D12
D13
D14
D15
CE2#
VS1
IORD#
IOWR#
NC
NC
NC
NC
NC
Vcc
NC
NC
NC
NC
CSEL#
VS2
RESET
Wait#
INPACK#
REG#
SPKR#
STSCHG#
D8
D9
D10
CD2#
GND
I/O
–
O
I/O
I/O
I/O
I/O
I
I
O
I
I
–
–
–
–
–
–
–
–
–
–
I
O
I
O
O
I
I/O
I/O
I/O
I/O
O
O
–
True IDE Mode
Signal Name
GND
CD1#
D11
D12
D13
D14
D15
CE2#
VS1
IORD#
IOWR#
NC
NC
NC
NC
NC
Vcc
NC
NC
NC
NC
CSEL#
VS2
RESET#
IORDY
INPACK#
REG#
DASP
PDIAG#
D8
D9
D10
CD2#
GND
I/O
–
O
I/O
I/O
I/O
I/O
I
I
O
I
I
–
–
–
–
–
–
–
–
–
–
I
O
I
O
O
I
I/O
I/O
I/O
I/O
O
O
–
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ACCESS SPECIFICATIONS
1. Attribute access specifications
WED7PxxxATA70xxI25
When CIS-ROM region or Configuration register region is accessed, read and write operations are executed under the
condition of REG# = ”L” as follows. That region can be accessed by Byte/Word/Odd-byte modes, which are defined by
PC card standard specifications.
Attribute Read Access Mode
Mode
Standby mode
Byte access (8bit)
Word access (16bit)
Odd byte access (8bit)
Note: X → L or H
REG#
X
L
L
L
L
CE2#
H
H
H
L
L
CE1#
H
L
L
L
H
A0
X
L
H
X
X
OE#
X
L
L
L
L
WE#
X
H
H
H
H
D8 to D15
High-Z
High-Z
High-Z
invalid
invalid
D0 to D7
High-Z
even byte
Invalid
even byte
High-Z
Attribute Write Access Mode
Mode
Standby mode
Byte access (8bit)
Word access (16bit)
Odd byte access (8bit)
Note: X → L or H
Write CIS-ROM region is invalid.
REG#
X
L
L
L
L
CE2#
H
H
H
L
L
CE1#
H
L
L
L
H
A0
X
L
H
X
X
OE#
X
H
H
H
H
WE#
X
L
L
L
L
D8 to D15
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
D0 to D7
Don’t care
even byte
Don’t care
even byte
Don’t care
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
2. Task File register access specifications
WED7PxxxATA70xxI25
There are two types of Task File register mapping, one is mapped I/O address area, the other is mapped Memory address
area. Each type of Task File register read and write operation is executed under the condition as follows. That area can
be accessed by Byte/Word/Odd Byte modes, which are defined by PC card standard specifications.
(1) I/O address map – Task File Register Read Access Mode (1)
Mode
Standby mode
Byte access (8bit)
Word access (16bit)
Odd byte access (8bit)
Note: X → L or H
REG#
X
L
L
L
L
CE2#
H
H
H
L
L
CE1#
H
L
L
L
H
A0
X
L
H
X
X
IORD#
X
L
L
L
L
IOWR#
X
H
H
H
H
OE#
X
H
H
H
H
WE#
X
H
H
H
H
D8 to D15
High-Z
High-Z
High-Z
odd byte
odd byte
D0 to D7
High-Z
even byte
odd byte
even byte
High-Z
Task File Register Write Access Mode (1)
Mode
Standby mode
Byte access (8bit)
Word access (16bit)
Odd byte access (8bit)
Note: X → L or H
REG#
X
L
L
L
L
CE2#
H
H
H
L
L
CE1#
H
L
L
L
H
A0
X
L
H
X
X
IORD#
X
H
H
H
H
IOWR#
X
L
L
L
L
OE#
X
H
H
H
H
WE#
X
H
H
H
H
D8 to D15
Don’t care
Don’t care
Don’t care
odd byte
odd byte
D0 to D7
Don’t care
even byte
odd byte
even byte
Don’t care
(2) Memory address map – Task File Register Read Access Mode (2)
Mode
Standby mode
Byte access (8bit)
Word access (16bit)
Odd byte access (8bit)
Note: X → L or H
REG#
X
H
H
H
H
CE2#
H
H
H
L
L
CE1#
H
L
L
L
H
A0
X
L
H
X
X
OE#
X
L
L
L
L
WE#
X
H
H
H
H
IORD#
X
H
H
H
H
IOWR#
X
H
H
H
H
D8 to D15
High-Z
High-Z
High-Z
odd byte
odd byte
D0 to D7
High-Z
even byte
odd byte
even byte
High-Z
Task File Register Write Access Mode (2)
Mode
Standby mode
Byte access (8bit)
Word access (16bit)
Odd byte access (8bit)
Note: X → L or H
REG#
X
H
H
H
H
CE2#
H
H
H
L
L
CE1#
H
L
L
L
H
A0
X
L
H
X
X
OE#
X
H
H
H
H
WE#
X
L
L
L
L
IORD#
X
H
H
H
H
IOWR#
X
H
H
H
H
D8 to D15
Don’t care
Don’t care
Don’t care
odd byte
odd byte
D0 to D7
Don’t care
even byte
odd byte
even byte
Don’t care
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
3. TRUE IDE MODE
WED7PxxxATA70xxI25
The card can be configured in a True IDE. This card is configured in this mode only when the OE# input signal is asserted
to GND by the host during power on . In this True IDE mode Attribute Registers are not accessible from the host. Only
I/O operation to the task file and data register is allowed. If this card is configured during power on sequence, data
register is accessed in word (16-bit). The card permits 8-bit accesses if the user issues a Set Feature Command to put
the device in 8-bit mode.
True IDE Mode Read I/O Function
Mode
Invalid mode
Standby mode
PIO Data register access
Multiword DMA Data register access
Alternate status access
Other task file access
Note: X → L or H
CE2#
L
H
H
H
L
H
CE1#
L
H
L
H
H
L
A0~A2
X
X
0
X
6H
1~7H
DMACK#
X
H
H
L
H
H
DIOR#
X
X
L
L
L
L
DIOW#
X
X
H
H
H
H
D8~D15
High-Z
High-Z
Odd byte
Odd byte
High-Z
High-Z
D0~D7
High-Z
High-Z
even byte
even byte
Status out
Data
True IDE Mode Write I/O Function
Mode
Invalid mode
Standby mode
PIO Data register access
Multiword DMA Data register access
Control register access
Other task file access
Note: X → L or H
CE2#
L
H
H
H
L
H
CE1#
L
H
L
H
H
L
A0~A2
X
X
0
X
6H
1~7H
DMACK#
X
H
H
L
H
H
DIOR#
X
X
H
H
H
H
DIOW#
X
X
L
L
L
L
D8~D15
Don’t care
Don’t care
Odd byte
Odd byte
Don’t care
Don’t care
D0~D7
Don’t care
Don’t care
even byte
even byte
Control in
Data
CARD SYSTEM PERFORMANCE
ITEM
Set up time (Reset to Ready)
Set up time (Power down to Ready)
Data transfer rate to / from host
Sustained read transfer rate
Sustained write transfer rate
Command to DRQ (Sector Re ad at Ready state)
Command to DRQ (Sector Write at Ready state)
Data transfer cycle end to ready (Sector write)
Auto Power down time
Notes:
1. The actual transfer rate is measured under ATA PIO mode 4 with single cycle time as 120ns.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
PERFORMANCE
250 ms (max.)
5.5 ms (max.)
16.6 M byte / s burst (max.), theoretically
6.5 M byte / s (max.), actually *1
6.0 M byte / s (max.), actually *1
4 ms (max.)
700 ms (max.)
2 ms (typ.), 200 ms (max.)
1.5s (min.), 1.8s (typ.)
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