Differential-to-LVDS Buffer/Divider
w/Internal Termination
8S89875I
Datasheet
Description
The 8S89875I is a high speed Differential-to-LVDS Buffer/Divider
w/Internal Termination. The 8S89875I has selectable ÷1, ÷2, ÷4, ÷8,
÷16 output divider. The clock input has internal termination resistors,
allowing it to interface with several differential signal types while
minimizing the number of required external components.
The device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
Features
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Two LVDS output pairs
Frequency divide select options: ÷1, ÷2, ÷4, ÷8, ÷16
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
Input frequency: 2.5GHz (maximum)
Cycle-to-cycle jitter, RMS: 4.1ps (maximum)
Total jitter: 18ps (maximum)
Output skew: 15ps (maximum)
Part-to-part skew: 280ps (maximum)
Propagation delay: 1000ps (maximum)
Full 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin compatible with the obsolete device, 889875AK
Block Diagram
S2
Pullup
Pin Assignment
16 15 14 13
12 IN
11 V
T
10 V
REF_AC
9 nIN
5
6
nc
V
DD
GND
S0
S1
Q0 1
nRESET/
nDISABLE
Pullup
nQ0
Enable
FF
2
Q1 3
nQ1 4
7
V
DD
8
nRESET/
nDISABLE
V
REF_AC
Enable
MUX
Q0
MUX
nQ0
8S89875I
16-Lead VFQFN
3mm x 3mm x 0.9mm package body
K Package
Top View
IN
50Ω
V
T
50Ω
÷2, ÷4,
÷8, ÷16
Q1
nQ1
nIN
S1
Pullup
Decoder
S0
Pullup
©2018 Integrated Device Technology, Inc
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8S89875I Datasheet
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 15, 16
6
7, 14
Name
Q0, nQ0
Q1, nQ1
S2, S1, S0
nc
V
DD
nRESET/
nDISABLE
nIN
V
REF_AC
V
T
IN
GND
Output
Output
Input
Unused
Power
Pullup
Type
Description
Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused outputs must be terminated
with 100
across the differential pair. LVDS interface levels.
Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused outputs must be terminated
with 100
across the differential pair. LVDS interface levels.
Select pins. Internal 37k
pullup resistor. Logic HIGH if left disconnected. Input
threshold is V
DD
/2. LVCMOS/LVTTL interface levels.
No connect.
Power supply pins.
Synchronizing enable/disable pin. When LOW, resets the divider (divided by 2, 4, 8 or
16 mode) and sets the Qx outputs to a logic 0. When HIGH, the dividers and Qx
outputs are enabled. The reset and disable function occurs on the next high-to-low
clock input transition. Input threshold is V
DD
/2V. Includes a 37k
pull-up resistor.
LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. R
T
= 50
termination to V
T
.
Reference voltage for AC-coupled applications. Equal to V
DD
– 1.35V (approx.).
Maximum sink/source current is 2mA.
Termination center-tap input.
Non-inverting LVPECL differential clock input.
R
T
= 50
termination to V
T
.
Power supply ground.
8
Input
Pullup
9
10
11
12
13
Input
Output
Input
Input
Power
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
©2018 Integrated Device Technology, Inc
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8S89875I Datasheet
Function Tables
Table 3A. Control Input Function Table
Input
nRESET
0
1 (default)
Q0, Q1
Disabled; LOW
Enabled
Outputs
nQ0, nQ1
Disabled; HIGH
Enabled
NOTE: After nRESET switches, the clock outputs are disabled or
enabled following a falling input clock edge as shown in
Figure 1.
V
DD
/2
nRESET
nIN
IN
V
IN
nQx
Qx
V
OUT
t
PD
t
RR
Figure 1. nRESET Timing Diagram
Table 3B. Truth Table
Inputs
nRESET/nDISABLE
1
1
1
1
1
0
(NOTE 1)
S2
0
1
1
1
1
X
S1
X
0
0
1
1
X
S0
X
0
1
0
1
X
Outputs
Q0, nQ0; Q1, nQ1
Reference Clock (pass through)
Reference Clock ÷2
Reference Clock ÷4
Reference Clock ÷8
Reference Clock ÷16 (default)
Qx = LOW, nQx = HIGH; Clock disabled
NOTE 1: nReset/nDisable function is asserted on the next clock input (IN, nIN) high-to-low transition.
©2018 Integrated Device Technology, Inc
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8S89875I Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
Input Sink/Source, I
REF_AC
Operating Temperature Range, T
A
Package Thermal Impedance,
JA
, (Junction-to-Ambient)
Storage Temperature, T
STG
NOTE: I
OUT
refers to output current supplied by the 8S89875I only.
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
±50mA
±100mA
±2mA
-40°C to +85°C
74.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
68
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
Test Conditions
Minimum
1.7
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
10
Units
V
V
µA
µA
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8S89875I Datasheet
Table 4C. Differential DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
I
IN
V
REF_AC
Parameter
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing
Differential Input Voltage Swing
Input Current
Bias Voltage
(IN, nIN)
V
DD
– 1.45
V
DD
– 1.35
(IN, nIN)
(IN, nIN)
(IN, nIN)
Test Conditions
Minimum
80
1.2
0
0.15
0.3
45
V
DD
– 1.25
Typical
100
Maximum
120
V
DD
+ 0.05
V
DD
– 0.15
1.2
Units
V
V
V
V
mA
V
Table 4D. LVDS DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OUT
V
OH
V
OL
V
OCM
V
OCM
Parameter
Output Voltage Swing
Output High Voltage
Output Low Voltage
Output Common Mode Voltage
Change in Common Mode Voltage
Test Conditions
Minimum
247
1.4
1.05
1.15
Typical
Maximum
454
1.95
1.55
1.45
50
Units
mV
V
V
V
mV
©2018 Integrated Device Technology, Inc
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