LD6805 series
T11
94-
1
Low-dropout regulators, high PSRR, 150 mA
Rev. 2 — 25 June 2012
Product data sheet
1. Product profile
1.1 General description
The LD6805 series is a small-size Low DropOut regulator (LDO) family with ultra high
Power Supply Rejection Ratio (PSRR) of 75 dB. The voltage drop is 250 mV at 150 mA
current rating.
Operating voltages can range from 2.3 V to 5.5 V. The devices are available with fixed
output voltages between 1.2 V to 3.6 V.
The LD6805K/xxH devices show a high-ohmic state at the output pin when set to disabled
mode. The LD6805K/xxP devices contain a pull-down switching transistor to provide a
low-ohmic output state (auto discharge function) in disabled mode.
The LD6805 series devices are available in a 1
1 mm DFN plastic package making them
ideal for use in portable applications requiring component miniaturization. All devices are
manufactured in monolithic silicon technology.
SO
1.2 Features and benefits
150 mA output current rating
75 dB PSRR at 1 kHz
Input voltage range 2.3 V to 5.5 V
Fixed output voltage between 1.2 V to 3.6 V
Dropout voltage 250 mV at 150 mA output rating
Low quiescent current in shutdown mode (typical 0.1
A)
40
V
RMS output noise voltage (typical value) at 10 Hz to 100 kHz
Turn-on time 150
s
LD6805K/xxH: high-ohmic (3-state) output state when disabled
LD6805K/xxP: low-ohmic output state when disabled (auto discharge function)
Integrated ESD protection up to 6 kV Human Body Model (HBM)
DFN1010C-4 (SOT1194-1) plastic package with a size of 1
1
0.55 mm
Pb-free, RoHS compliant and free of halogen and antimony (dark green compliant)
1.3 Applications
Analog and digital interfaces requiring lower than standard supply voltages in mobile
appliances such as smart phones, mobile phone handsets and cordless telephones.
Other typical applications are digital still cameras, mobile internet devices, personal
navigation devices and portable media players.
NXP Semiconductors
LD6805 series
Low-dropout regulators, high PSRR, 150 mA
2. Pinning information
2.1 Pinning
LD6805
IN
4
3
EN
OUT
1
2
GND
001aan948
Transparent top view
Fig 1.
Pin configuration for DFN1010C-4 (SOT1194-1)
2.2 Pin description
Table 1.
Symbol
OUT
GND
EN
IN
i.c.
[1]
Pin description for DFN1010C-4 (SOT1194-1)
Pin
1
2
3
4
TAB
Description
regulator output voltage
supply ground
device enable input; active HIGH
regulator input voltage
internal connected
[1]
The TAB is GND level (it is placed on the reverse side of the IC).
It is recommended to connect the TAB to GND. Leaving it unconnected is also allowed but it may result in
lower thermal performance.
3. Ordering information
Table 2.
Ordering information
Package
Name
LD6805 series
DFN1010C-4
Description
plastic thermal enhanced ultra thin small outline package;
no leads; 4 terminals; body 1
1
0.55 mm
Version
SOT1194-1
Type number
LD6805_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 25 June 2012
2 of 20
NXP Semiconductors
LD6805 series
Low-dropout regulators, high PSRR, 150 mA
3.1 Ordering options
Further information on output voltage is available on request; see
Section 20 “Contact
information”.
Table 3.
Type number extension of high-ohmic output
Nominal output
voltage
1.2 V
1.3 V
1.4 V
1.5 V
1.6 V
1.8 V
1.85 V
2.0 V
2.1 V
Type number
LD6805K/22H
LD6805K/23H
LD6805K/25H
LD6805K/28H
LD6805K/29H
LD6805K/30H
LD6805K/31H
LD6805K/33H
LD6805K/36H
Nominal output
voltage
2.2 V
2.3 V
2.5 V
2.8 V
2.9 V
3.0 V
3.1 V
3.3 V
3.6 V
Type number
LD6805K/12H
LD6805K/13H
LD6805K/14H
LD6805K/15H
LD6805K/16H
LD6805K/18H
LD6805K/185H
LD6805K/20H
LD6805K/21H
Table 4.
Type number extension of pull-down output
Nominal output
voltage
1.2 V
1.3 V
1.4 V
1.5 V
1.6 V
1.8 V
2.0 V
2.1 V
2.2 V
Type number
LD6805K/23P
LD6805K/25P
LD6805K/28P
LD6805K/29P
LD6805K/30P
LD6805K/31P
LD6805K/33P
LD6805K/36P
-
Nominal output
voltage
2.3 V
2.5 V
2.8 V
2.9 V
3.0 V
3.1 V
3.3 V
3.6 V
-
Type number
LD6805K/12P
LD6805K/13P
LD6805K/14P
LD6805K/15P
LD6805K/16P
LD6805K/18P
LD6805K/20P
LD6805K/21P
LD6805K/22P
LD6805_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 25 June 2012
3 of 20
NXP Semiconductors
LD6805 series
Low-dropout regulators, high PSRR, 150 mA
4. Block diagram
V
IN
V
OUT
R1
V
EN
V
reference
GENERATOR
OVER CURRENT
PROTECTION
R2
ENABLE SHUT
DOWN CIRCUIT
GND
001aan755
Fig 2.
Block diagram of LD6805K/xxP (auto discharge function)
V
IN
V
OUT
R1
V
EN
V
reference
GENERATOR
OVER CURRENT
PROTECTION
R2
ENABLE SHUT
DOWN CIRCUIT
GND
001aan873
Fig 3.
Block diagram of LD6805K/xxH
LD6805_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 25 June 2012
4 of 20
NXP Semiconductors
LD6805 series
Low-dropout regulators, high PSRR, 150 mA
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
IN
P
tot
T
stg
T
j
T
amb
V
ESD
Parameter
voltage on pin IN
total power dissipation
storage temperature
junction temperature
ambient temperature
electrostatic discharge voltage
human body model level 6
machine model class 3
[1]
[2]
[3]
[2]
[3]
Conditions
4 ms transient
[1]
Min
0.5
-
55
40
40
-
-
Max
+6.0
400
+150
+125
+85
6
400
Unit
V
mW
C
C
C
kV
V
The (absolute) maximum power dissipation depends on the junction temperature T
j
. Higher power dissipation is allowed with lower
ambient temperatures. The conditions to determine the specified values are T
amb
= 25
C
and the use of a two layer PCB.
According to IEC 61340-3-1.
According to JESD22-A115C.
6. Recommended operating conditions
Table 6.
Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
T
amb
T
j
Pin IN
V
IN
Pin EN
V
EN
Pin OUT
C
L(ext)
[1]
Parameter
ambient temperature
junction temperature
voltage on pin IN
voltage on pin EN
external load capacitance
Conditions
Min
40
-
2.3
0
[1]
Typ
-
-
-
-
1.0
Max
+85
+125
5.5
V
IN
-
Unit
C
C
V
V
F
0.7
See
Section 10.1 “Output capacitor values”.
7. Thermal characteristics
Table 7.
Symbol
R
th(j-a)
[1]
Thermal characteristics
Parameter
thermal resistance from junction to ambient
Conditions
[1][2]
Typ
250
Unit
K/W
The overall R
th(j-a)
can vary depending on the board layout. To minimize the effective R
th(j-a)
, all pins must have a solid connection to
larger Cu layer areas for example to the power and ground layer. In multi-layer PCB applications, the second layer is used to create a
large heat spreader area directly below the LDO. If this layer is either ground or power, it is connected with several vias to the top layer
connecting to the device ground or supply. Avoid the use of solder-stop varnish under the chip.
Use the measurement data given for a rough estimation of the R
th(j-a)
in your application. The actual R
th(j-a)
value can vary in applications
using different layer stacks and layouts.
[2]
LD6805_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 25 June 2012
5 of 20
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