W3EG72255MS133JD3SG datasheet, PDF

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W3EG72255MS133JD3SG: Description2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL; File Size249KB，15 Pages; ManufacturerWhite Electronic Designs Corporation; Websitehttp://www.wedc.com/

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W3EG72255MS133JD3SG Overview

2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL

W3EG72255MS133JD3SG Preview

White Electronic Designs

W3EG72255S-D3

-JD3

-AJD3

PRELIMINARY*

2GB – 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL

FEATURES

Double-data-rate architecture

DDR200, DDR266 and DDR333:

• JEDEC design speciﬁcations

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input.

Auto and self refresh

Serial presence detect

Dual Rank

Power supply: V

CC =

2.5V ± 0.2V

JEDEC standard 184 pin DIMM package

• Package height options:

JD3: 30.48mm (1.2"),

AJD3: 28.70mm (1.13")

NOTE: Consult factory for availability of:

• RoHS compliant products

• Vendor source control options

• Industrial temperature option

* wThis product is under development, is not qualiﬁed or characterized and is subject

to change without notice.

DESCRIPTION

The W3EG72255S is a 2x128Mx72 Double Data Rate

SDRAM memory module based on 512Mb DDR SDRAM

components. The module consists of eighteen 256Mx4

stacks, in 66 pin TSOP packages mounted on a 184 pin

FR4 substrate.

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible

on both edges and Burst Lengths allow the same

device to be useful for a variety of high bandwidth, high

performance memory system applications.

OPERATING FREQUENCIES

DDR333 @CL=2.5

Clock Speed

CL-t

RCD

-t

166MHz

2.5-3-3

DDR266 @CL=2

133MHz

2-2-2

DDR266 @CL=2

133MHz

2-3-3

DDR266 @CL=2.5

133MHz

2.5-3-3

DDR200 @CL=2

100MHz

2-2-2

November 2004

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

PIN CONFIGURATION

SYMBOL

REF

DQ0

DQ1

DQS0

DQ2

DQ3

RESET#

DQ8

DQ9

DQS1

CCQ

DQ10

DQ11

CKE0

CCQ

DQ16

DQ17

DQS2

DQ18

CCQ

DQ19

DQ24

DQ25

DQS3

DQ26

DQ27

CB0

CB1

SYMBOL

DQS8

CB2

CB3

BA1

DQ32

CCQ

DQ33

DQS4

DQ34

BA0

DQ35

DQ40

CCQ

WE#

DQ41

CAS#

DQS5

DQ42

DQ43

DQ48

DQ49

CCQ

DQS6

DQ50

DQ51

CCID

DQ56

DQ57

DQS7

DQ58

DQ59

SDA

SCL

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

SYMBOL

DQ4

DQ5

CCQ

DQS9

DQ6

DQ7

CCQ

DQ12

DQ13

DQS10

DQ14

DQ15

CKE1

CCQ

DQ20

A12

DQ21

A11

DQS11

DQ22

DQ23

DQ28

DQ29

CCQ

DQS12

DQ30

DQ31

CB4

CB5

CCQ

CK0

CK0#

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

SYMBOL

DQS17

A10

CB6

CCQ

CB7

DQ36

DQ37

DQS13

DQ38

DQ39

DQ44

RAS#

DQ45

CCQ

CS0#

CS1#

DQS14

DQ46

DQ47

CCQ

DQ52

DQ53

DQS15

DQ54

DQ55

CCQ

DQ60

DQ61

DQS16

DQ62

DQ63

CCQ

SA0

SA1

SA2

CCSPD

A0-A12

BA0-BA1

DQ0-DQ63

CB0-CB7

DQS0-DQS17

CK0

CK0#

CKE0, CKE1

CS0#, CS1#

RAS#

CAS#

WE#

CCQ

REF

CCSPD

SDA

SCL

SA0-SA2

CCID

RESET#

W3EG72255S-D3

-JD3

-AJD3

PRELIMINARY

PIN NAMES

Address input (Multiplexed)

Bank Select Address

Data Input/Output

Check bits

Data Strobe Input/Output

Clock Input

Clock Enable input

Chip Select Input

Row Address Strobe

Column Address Strobe

Write Enable

Power Supply

Power Supply for DQS

Ground

Power Supply for Reference

Serial EEPROM Power Supply

Serial data I/O

Serial clock

Address in EEPROM

Indentiﬁcation Flag

No Connect

Reset Enable

November 2004

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

FUNCTIONAL BLOCK DIAGRAM

RCS1#

RCS0#

W3EG72255S-D3

-JD3

-AJD3

PRELIMINARY

DQS0

DQ0

DQ1

DQ2

DQ3

DQS1

DQ8

DQ9

DQ10

DQ11

DQS2

DQ16

DQ17

DQ18

DQ19

DQS3

DQ24

DQ25

DQ26

DQ27

DQS4

DQ32

DQ33

DQ34

DQ35

DQS5

DQ40

DQ41

DQ42

DQ43

DQS6

DQ48

DQ49

DQ50

DQ51

DQS7

DQ56

DQ57

DQ58

DQ59

DQS8

CB0

CB1

CB2

CB3

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS# DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS# DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS# DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS9

DQ4

DQ5

DQ6

DQ7

DQS10

DQ12

DQ1

DQ13

DQ14

DQ15

DQS11

DQ20

DQ21

DQ2

DQ22

DQ23

DQS12

DQ28

DQ29

DQ30

DQ31

DQS13

DQ36

DQ37

DQ38

DQ39

DQS14

DQ44

DQ45

DQ46

DQ47

DQS15

DQ52

DQ53

DQ54

DQ55

DQS16

DQ60

DQ61

DQ62

DQ63

DQS17

CB4

CB5

CB6

CB7

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS#

CCSPD

SPD

CK0

PLL

CK0#

SDRAM

CCQ

DDR SDRAMs

REF

DDR SDRAMs

CS0#

CS1#

BA0,BA1

A0-A12

RAS#

CAS#

CKE0

CKE1

WE#

DDR SDRAMs

RCS0#

RCS1#

RBA0,RBA1

RA0-RA12

RRAS#

RCAS#

RCKE0

RCKE1

RWE#

BA0,BA1: DDR SDRAMs

A0-A12: DDR SDRAMs

RAS#: DDR SDRAMs

CAS#: DDR SDRAMs

CKE: DDR SDRAMs

WE#: DDR SDRAMs

SERIAL PD

SCL

SDA

SA0

SA1

SA2

PCK

PCK#

RESET#

NOTE: All resistor values are 22 ohms unless otherwise speciﬁed

Notes:

DQ-to-I/O wiring is shown as recommended but may be changed.

DQ/DQS/DM/CKE/S relationships must be maintained as shown.

November 2004

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to V

Voltage on V

supply relative to V

Storage Temperature

Power Dissipation

Short Circuit Current

Symbol

, V

OUT

, V

CCQ

STG

W3EG72255S-D3

-JD3

-AJD3

PRELIMINARY

Value

-0.5 - 3.6

-1.0 - 3.6

-55 - +150

Units

°C

Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability

DC CHARACTERISTICS

0°C

≤

70°C, V

= 2.5V ± 0.2V

Parameter

Supply Voltage

Reference Voltage

Termination Voltage

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Symbol

CCQ

REF

Min

2.3

1.15

REF

+ 0.15

-0.3

+ 0.76

—

Max

2.7

1.35

CCQ

+ 0.3

REF

- 0.15

—

- 0.76

Unit

CAPACITANCE

= 25°C, f = 1MHz, V

= 2.5V ± 0.2V

Parameter

Input Capacitance (A0-A12)

Input Capacitance (RAS#, CAS#, WE#)

Input Capacitance (CKE0)

Input Capacitance (CK0,CK0#)

Input Capacitance (CS0#)

Input Capacitance (DQM0-DQM8)

Input Capacitance (BA0-BA1)

Data input/output capacitance (DQ0-DQ63)(DQS)

Data input/output capacitance (CB0-CB7)

Symbol

IN1

IN2

IN3

IN4

IN5

IN6

IN7

OUT

Max

6.25

5.5

6.25

13.0

6.25

13.0

Unit

November 2004

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

SPECIFICATIONS AND TEST CONDITIONS

0°C

≤

+70°C, V

CCQ

= 2.5V ± 0.2V, V

= 2.5V ± 0.2V.

Includes DDR SDRAM components only

DDR333@CL=2.5

Max

4140

W3EG72255S-D3

-JD3

-AJD3

PRELIMINARY

Parameter

Operating Current

Symbol

DD0

Rank 1

Conditions

One device bank; Active - Precharge; t

= t

(MIN); t

= t

(MIN); DQ,DM and

DQS inputs changing once per clock cycle;

Address and control inputs changing once

every two cycles.

One device bank; Active-Read-Precharge

Burst = 2; t

= t

(MIN); t

= t

(MIN);

OUT

= 0mA; Address and control inputs

changing once per clock cycle.

All device banks idle; Power-down mode;

= t

(MIN); CKE = (low)

CS# = High; All device banks idle;

= t

(MIN); CKE = High; Address

and other control inputs changing once

per clock cycle. V

= V

REF

for DQ, DQS

and DM.

One device bank active; Power-Down

mode; t

(MIN); CKE = (low)

CS# = High; CKE = High; One device

bank; Active-Precharge;t

= t

RAS

(MAX);

= t

(MIN); DQ, DM and DQS inputs

changing twice per clock cycle; Address

and other control inputs changing once per

clock cycle.

Burst = 2; Reads; Continuous burst; One

device bank active; Address and control

inputs changing once per clock cycle; t

(MIN); l

OUT

= 0mA.

Burst = 2; Writes; Continuous burst; One

device bank active; Address and control

inputs changing once per clock cycle;

= t

(MIN); DQ,DM and DQS inputs

changing once per clock cycle.

= t

(MIN)

CKE

≤

0.2V

Four bank interleaving Reads (BL=4)

with auto precharge with t

(MIN);

(MIN); Address and control inputs

change only during Active Read or Write

commands.

DDR266:@CL=2, 2.5

Max

4140

DDR200@CL=2

Max

4140

Units

Rank 2

Standby

State

DD3N

Operating Current

DD1

4680

DD3N

Precharge Power-

Down Standby Current

Idle Standby Current

DD2P

DD2F

180

1620

180

1620

180

1620

rnA

DD2P

DD2F

Active Power-Down

Standby Current

Active Standby Current

DD3P

DD3N

1260

1800

1260

1800

1260

1800

DD3P

DD3N

Operating Current

DD4R

4770

DD3N

Operating Current

DD4W

4590

rnA

DD3N

Auto Refresh Current

Self Refresh Current

Operating Current

DD5

DD6

DD7A

7020

180

9090

7020

180

9000

7020

180

9000

DD3N

DD6

DD3N

November 2004

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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