PD70101 / PD70201
Datasheet
Power Over Ethernet
802.3af/at PD Controller
The PD70101 and PD70201 are integrated Powered Device Interface and
PWM controllers for a DC-DC converter used in IEEE802.3af and
IEEE802.3at applications. The PD70101 can be used for IEEE802.3af or
IEEE802.3at Type 1 applications, while the PD70201 can also be used in
IEEE802.3at Type 2 applications.
A single PD70201 can be used in 4-pair applications which consumes up
to 47.7W.
These devices have a number of features designed to improve efficiency
and reliability:
Detection and Classification:
The front end interface includes detection
and classification circuitry. The detection signature resistor is
disconnected upon completion of the detection phase. The system then
begins the classification phase. Classification can be configured for
Classes 0 to 4 via an external resistor. The PD70201 includes a
two-events classification identification circuit which generates a flag to
inform the PD application whether the Power Source Equipment (PSE) is
Type 1 or Type 2.
Capacitor:
A current limited internal MOSFET switch charges the input
capacitor of the DC-DC converter. This capacitor is discharged in a timely
manner when the input power is removed.
Gate drivers:
The PWM DC-DC controller has two built-in gate drivers
designed to swing between VCC and GND. These 2 out-of-phase driver
stages can be configured for synchronous rectification or active clamp.
Peak current mode control:
The DC-DC converter employs peak current
mode control for better line and load step response. The switching
frequency can be set from 100kHz to 500kHz, enabling a size and
efficiency trade off.
Maximum duty cycle
is limited to 50% to reduce the power MOSFET
switch voltage to two times the input voltage; a 150V rated MOSFET can
be used for the primary side switch. The secondary synchronous
MOSFET voltage rating depends on the output voltage and can be higher
or lower than the primary side MOSFET switch.
Soft-start circuit:
The devices include a soft-start circuit to control the
output voltage rise time (user settable) at start up, and to limit the inrush
current. An integrated startup bias circuit powers the DC-DC controller,
until the device starts up by the voltage generated by the bootstrap circuit.
Low Voltage Protection Warning and Monitoring:
Dual Under Voltage
Lock Out (UVLO), which monitors both the PoE Port Input Voltage and
VCC, ensures reliable operation during any system disturbances. The
PoE port UVLO has a programmable threshold and hysteresis to enable
tailoring to the desired turn on and turn off voltage.
An internal current sense amplifier with a Kelvin connection allows the use
of an extremely low resistor to measure the current sense threshold
voltage (200 mV) which optimizes efficiency.
Low Power Mode operation is provided to improve efficiency under light
loads such as when the PD is in standby. The user can define at what
power level the unit enters low power mode by means of a single resistor
value.
Features
IEEE802.3af and IEEE802.3at
Compliant
Support for 4-pair Applications of up to
47.7W With a Single IC
Two-events Classification
Identification With a Level Signal
Indicating Type 1 or Type 2 PSE
Less Than 10 µA (typical) Offset
Current During Detection
Signature Resistor is Disconnected
upon Detection
Programmable Classification Setting
With a Single Resistor
Integrated 0.6 Ohm Isolating MOSFET
Switch With Inrush Current Limit
Power Off DC-DC Input Capacitor
Discharge
100 kHz to 500 kHz Adjustable DC-DC
Switching Frequency
DC-DC Frequency Can Be
Synchronized to External Clock
Supports Low Power Mode Operation
for Higher Efficiency 50% Maximum
Duty Cycle
Soft-start Circuit to Control The Output
Voltage Rise Time
Two out-of-phase driver stages for
efficient synchronous rectification or
active clamp
PoE Port Input UVLO with
Programmable Threshold and
Hysteresis
Internal Differential Amplifier
Simplifying Non-isolated Step Down
Converter
Over Load and Short Circuit Protection
RoHS Compliant & Pb-Free
Applications
IEEE802.3at and IEEE802.3af
powered devices such as IP
phones, WLAN Access Points and
Network Cameras.
48V Input Telcom/Networks Hot
Swappable Power Supply.
_________________________________________________________________________________________________________
Copyright © 2016
Microsemi
Page 1 of 20
Rev.2.0, 17-Jan-2017
CPG – PoE BU
One Enterprise Aliso Viejo, CA 92656 USA
PD70101 / PD70201
Datasheet
Pin Configuration
PGND
VAUX
31
PGND
VAUX
VCC
30
CSN
CSP
VPP
32
VCC
CSN
CSP
VPP
PG
28
VH
29
PG
VH
27
26
25
24
23
22
32
31
30
29
28
27
26
25
24
23
22
RDET
PGOOD
RREF
RCLASS
VPN_IN
N/C
N/C
VPN_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SG
VL
GND
FB
DAO
COMP
VSP
VSN
RDET
PGOOD
RREF
RCLASS
VPN_IN
N/C
AT_FLAG*
VPN_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SG
VL
GND
FB
DAO
COMP
VSP
VSN
MSC
70101
YYWWX
21
20
19
18
17
MSC
70201
YYWWX
21
20
19
18
17
N/C
ENABLE
VINS
HYST
SYNC
RFREQ
SS
RCLP
Ordering Information
Ambient Temperature
Type
Package
Part Number
Packaging Type
-40°C to 85°C
Pin Description
Pin
Number
1
2
3
4
PD70101
Pin Name
RDET
PGOOD
RREF
RCLASS
PD70201
Pin Name
RDET
PGOOD
RREF
RCLASS
Description
Valid Detection Resistor: Connect a 24.9kΩ, 1% resistor from this pin to
VPP.
Open Drain Output (active low): This flag is generated to indicate the
power rails (VPN_OUT) are ready.
Bias current resistor for the PD Interface. Connect a 240k 1% resistor
between this pin and VPN_IN.
Power Classification Setting: Connect external class resistor between
this pin and VPN_IN.
_________________________________________________________________________________________________________
Copyright © 2015
Microsemi
Page 2 of 20
Rev.2.0, 17-Jan-2017
CPG – PoE BU
One Enterprise Aliso Viejo, CA 92656 USA
N/C
ENABLE
VINS
HYST
RoHS2 compliant,
Pb-free
Matte Tin Pin Finish
QFN 5x5 Plastic 32 pin
SYNC
RFREQ
SS
RCLP
Figure 1 ·
Pinout QFN Package(Top View)
YYWWX = Year /Week / lot code
PD70101ILQ (IEEE802.3af)
PD70101ILQ-TR (IEEE802.3af)
PD70201ILQ (IEEE802.3at)
PD70201ILQ-TR (IEEE802.3at)
Bulk / Tube
Tape and Reel
Bulk / Tube
Tape and Reel
PD70101 / PD70201
Datasheet
Pin
Number
5
6
7
8
9
10
PD70101
Pin Name
VPN_IN
N/C
N/C
VPN_OUT
N/C
ENABLE
PD70201
Pin Name
VPN_IN
N/C
AT_FLAG
VPN_OUT
N/C
ENABLE
Description
VPort Negative Input: Connected to the isolating switch input N-channel
MOSFET source.
Not Used.
Open Drain Output (active low): This flag indicates if the chip detects an
IEEE 802.3at compliant PSE.
VPort Negative Output: Connected to the isolating switch output. N-
channel MOSFET Drain.
Not Used.
Logic level Enable input for DC-DC controller. Pulling this pin to VL turns
on the DC-DC controller. This allows the DC-DC controller to be turned
on without power to the PD interface.
VPP input voltage sensing for UVLO comparator. Connect to an external
resistor divider from VPP to GND. Threshold is 1.2V reference.
Output of the VINS/UVLO comparator. This pin is used for VPP UVLO
hysteresis programming.
External Clock synchronization for the DC-DC controller. Connect an
external clock as defined in the EC table to this pin to synchronize the
DC-DC converter switching frequency to this clock. PG rising edge is
synchronized with the clock rising edge.
DC-DC Switching Frequency Setting. Connect a resistor from this pin to
GND to set the switching frequency.
Soft-start: Connect a capacitor from this pin to GND to set the soft-start
time of the DC-DC converter. This capacitor is charged with an internal
current source to 1.2V.
Low Power Mode Clamp. Connect a resistor from this pin to GND to
program the LPM clampimg voltage or connect this pin to GND to disable
LPM.
Differential Amplifier's negative input. Connect this to the junction of a
resistor divider from Vo- to GND for the Direct Buck converter
application.
Differential Amplifier's positive input. Connect this to the junction of a
resistor divider from Vo+ to GND for the Direct Buck converter
application.
Error Amplifier Output. Short to FB pin when driven directly with an
optoisolator for Isolated DC-DC Converter. Connect to FB via RC
compensation networks for Non-Isolated Direct Buck Converter.
Differential Amplifier Output. Connect to FB (externally) for Non-Isolated
Direct Buck Converter.
Inverting Input of the Error Amplifier. Connect to opto-coupler for Isolated
DC-DC. Connect to RC compensation networks for Non-isolated DC-DC
This is Analog GND. Connect to a local AGND plane. Soft-start capacitor
and the frequency setting resistor return to this local GND plane.
11
12
VINS
HYST
VINS
HYST
13
SYNC
SYNC
14
RFREQ
RFREQ
15
SS
SS
16
RCLP
RCLP
17
VSN
VSN
18
VSP
VSP
19
COMP
COMP
20
21
22
DAO
FB
GND
DAO
FB
GND
_________________________________________________________________________________________________________
Copyright © 2015
Microsemi
Page 3 of 20
Rev.2.0, 17-Jan-2017
CPG – PoE BU
One Enterprise Aliso Viejo, CA 92656 USA
PD70101 / PD70201
Datasheet
Pin
Number
23
24
PD70101
Pin Name
VL
SG
PD70201
Pin Name
VL
SG
Description
5V (GND reference) internal LDO Output. Connect a 1µF or higher
ceramic cap from VL to GND.
Secondary Gate Driver. Output is the compliment of PG output. Leave
open (NC) if not used. SG is low when in Low Power Skip Mode.
This is the Power Ground. Connect to a local PGND plane. Input, VCC
decoupling capacitors, PG and SG drivers. Primary current sense
resistor return to this PGND.
Negative Input of the Current Sense Amplifier. Kelvin connect to the
PGND side of the primary current sense resistor.
Possitive Input of the Current Sense Amplifier. Kelvin connect to the Non-
PGND side of the primary current sense resistor.
Primary Gate Driver. Connect to the gate of the primary side Power
MOSFET, directly or via a resistor.
5V High side ( VCC reference) internal LDO Output. Connect a 0.1µF or
higher ceramic cap from VH to VCC.
Input Supply to the DC-DC Controller. Connect a 4.7µF or higher ceramic
capacitor from this pin to PGND. Alternately an parallel combination of
1µF ceramic and an greater than 10µF electrolytic capacitor can be used.
Auxiliary voltage reference to VPN_OUT; this voltage can be used for
DC-DC startup when operated with a bootstrapped voltage source. For
applications with POE power only connect directly to VCC; for
applications using multiple power sources (such as a wall adaptor),
connect to VCC pin through a small, low current, 30V rated schottky
diode.
This is the positive terminal of the POE input port. Connect to the positive
terminal of the input bridges at the CDET positive side.
Thermal Pad; electrically connected to VPN_IN. For proper thermal
management should be tied to a large copper fill or plane that is
electrically connected to VPN_IN.
25
PGND
PGND
26
27
28
29
CSN
CSP
PG
VH
CSN
CSP
PG
VH
30
VCC
VCC
31
VAUX
VAUX
32
VPP
VPP
EP
Exposed Pad
Exposed Pad
_________________________________________________________________________________________________________
Copyright © 2015
Microsemi
Page 4 of 20
Rev.2.0, 17-Jan-2017
CPG – PoE BU
One Enterprise Aliso Viejo, CA 92656 USA
PD70101 / PD70201
Datasheet
Absolute Maximum Ratings
Parameter
VPP, RDET, VPN_OUT (with respect to VPN_IN)
RREF, RCLASS (with respect to VPN_IN)
PGOOD, AT_FLAG, VAUX (with respect to VPN_OUT)
VCC (with respect to PGND)
PG, SG (with respect to PGND)
VL, VSN, VSP (with respect to PGND)
VH (with respect to VCC)
All Other Pins (with respect to GND)
ESD (HBM) Protection at all I/O pins*
Maximum Junction Temperature (T
JMAX
)
Operational Ambient Temperature
Storage Temperature Range
Peak Package Solder Reflow Temperature (40 seconds maximum
exposure), MSL3
Value
-0.3V to 74
-0.3V to 6
-0.3V to 74
-0.3V to 40
-0.3V to 20
-0.3V to 6
-0.3V to VCC - 6
-0.3V to VL + 0.3
±
1
+150
-40 to +85
-65 to +150
260
Units
V
DC
V
W
V
DC
V
DC
V
V
DC
V
DC
kV
°C
°C
°C
°C
Exceeding these ratings could cause damage to the device. All voltages are with respect to VPNIN. Currents are positive into, negative out of specified
terminal. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under
“Recommended Operating Conditions” are not implied. Exposure to “Absolute Maximum Ratings” for extended periods may affect device reliability. *All
pins except pin 2 (PGOOD) and pin 31 (VAUX). Pin 2 & 31 ESD Protection ±150V HBM
.
Thermal Properties
Thermal Resistance
θ
JC
Junction to Case
θ
JP
Junction to Pad
θ
JA
Junction to Ambient
Typ
5
4
23
°C/W
Units
Note:
The
Jx
numbers assume no forced airflow. Junction Temperature is calculated using T
J
= T
A
+ (PD x
J
A
). In
particular, θJ
A
is a function of the PCB construction. The stated number above is for a four-layer board in
accordance with JESD-51 (JEDEC) with thermal vias.
Electrical Characteristics
Symbol
Parameter
Test Conditions / Comment
PD70101 & PD70201
Min
Typ
Max
Units
Unless otherwise specified, the following specifications apply over the operating ambient temperature of -40
°
C ≤ T
A
≤ 85
°
C except where otherwise
noted with the following test conditions: V
PP
= 48V; V
EN
= HIGH, f
s
= 250 kHz. Production tests performed at 25
°
C. Unless otherwise specified V
PP
is
with respect to VPN_IN, VCC is with respect to PGND.
PD Interface
Power Supply
V
PP
Input Voltage
0
55
57
V
_________________________________________________________________________________________________________
Copyright © 2015
Microsemi
Page 5 of 20
Rev.2.0, 17-Jan-2017
CPG – PoE BU
One Enterprise Aliso Viejo, CA 92656 USA
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