White Electronic Designs
32Mx72 DDR SDRAM
FEATURES
Data rate = 200, 250, 266, 333Mbs
Package:
• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) pins for masking write data
(one per byte)
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military
TemperatureRanges
Organized as 32M x 72
Weight: W3E32M72S-XSBX - 2.5 grams typical
W3E32M72S-XSBX
BENEFITS
73% Space Savings vs. TSOP
• 44% Space Savings vs FPBGA
Reduced part count
37% I/O reduction vs TSOP
• 31% I/O reduction vs FPBGA
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 64M x 72 density (contact factory
for information)
GENERAL DESCRIPTION
The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
The 256MB DDR SDRAM uses a double data rate
ar chi tec ture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 256MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at the
receiver.strobe transmitted by the DDR SDRAM during
READs and by the memory contoller during WRITEs. DQS
is edge-aligned with data for READs and center-aligned
with data for WRITEs. Each chip has two data strobes, one
for the lower byte and one for the upper byte.
The 256MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
* This product is subject to change without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2006
Rev. 6
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
DENSITY COMPARISONS
TSOP Approach (mm)
11.9
11.9
11.9
11.9
11.9
W3E32M72S-XSBX
Actual Size
W3E32M72S-XSBX
22
22.3
66
TSOP
66
TSOP
66
TSOP
66
TSOP
66
TSOP
16
S
A
V
I
N
G
S
73%
37%
Area
I/O
Count
5 x 265mm
2
= 1325mm
2
5 x 66 pins = 330 pins
352mm
2
208 Balls
Actual Size
W3E32M72S-XSBX
10.0
60
FBGA
22
CSP Approach (mm)
10.0
60
FBGA
10.0
60
FBGA
10.0
60
FBGA
10.0
60
FBGA
12.5
16
S
A
V
I
N
G
S
44%
31%
Area
I/O
Count
5 x 125mm
2
= 625mm
2
5 x 60 balls = 300 balls
352mm
2
208 Balls
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
The pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-
July 2006
Rev. 6
saving power-down mode. All inputs are compatible with
the Jedec Standard for SSTL_2. All full drive options
outputs are SSTL_2, Class II compatible.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register definition,
command descriptions and device operation.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIG. 1 PIN CONFIGURATION
W3E32M72S-XSBX
T
OP
V
IEW
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
VCCQ
2
VCC
3
VSS
4
VCCQ
5
VCCQ
6
VSS
7
VCCQ
8
VCCQ
9
VSS
10 11
VCC
VSS
VSS
CS2
CS0
CKE2
CKE0
CAS2
RAS0
RAS2
VSS
VCCQ
VSS
CK0
CK2
CK0
CK2
DQML0
DQML2
CAS0
WE0
WE2
VSS
DQMH2
DQMH0
DQSH2
DQSH0
DQ8
DQ40
DQ5
DQ39
DQ7
DQSL2
DQSL0
DQ41
DQ9
DQ10
DQ42
DQ43
DQ12
DQ3
DQ36
DQ4
DQ38
DQ6
DQ44
DQ11
DQ13
DQ45
DQ14
DQ33
DQ1
DQ34
DQ2
DQ37
DQ35
DQ64
DQ65
DQ15
DQ47
DQ46
VSS
DQ32
DQ0
DQ77
DQ79
DQ78
DNU
DQ66
DQ69
DNU
DQ67
VCC
DQ72
DQ73
DQ74
DQ75
DQ76
VCCQ
A12
BA1
A0
VCC
VSS
VCCQ
A7
A9
DNU*
VCC
VSS
A10
A3
VCCQ
VSS
VREF
VSS
VCCQ
A4
A11
VSS
VCC
A2
BA0
A1
VCCQ
VSS
VCC
A6
A8
A5
VCCQ
DQ71
DQ70
DQSL4
DQML4
DQ68
VCC
DQSH4
DQMH4
CK4#
CK4
DNU
WE4#
CAS4#
RAS4#
DQ16
DQ48
VSS
DQ63
DQ31
DQ62
CKE4
CS4#
DQ22
DQ52
DQ18
DQ50
DQ17
DQ49
DQ30
DQ61
DQ29
DQ59
DQ27
DQ23
DQ54
DQ21
DQ19
DQ51
DQ60
DQ28
DQ58
DQ26
DQ57
DQ25
DQSL1
DQSL3
DQ55
DQ53
DQ20
DQ56
DQ24
DQMH3
DQMH1
DQSH1
DQSH3
VSS
CAS3
WE3#
WE1#
DQML3
DQML1
CK1
CK3
CK1
CK3
VSS
VCCQ
VSS
CAS1#
RAS3#
RAS1#
CKE1
CKE3
CS1
CS3
VSS
VCCQ
VSS
VCC
VSS
VCCQ
VCCQ
VSS
VCCQ
VCCQ
VSS
VCC
VSS
* pin J10 is reserved for signal A13 on future upgrades.
NOTE: DNU = Do Not Use.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2006
Rev. 6
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIG. 2 FUNCTIONAL BLOCK DIAGRAM
WE
0
#
RAS
0
#
CAS
0
#
WE# RAS# CAS#
V
REF
A
0-12
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
W3E32M72S-XSBX
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Power
must first be applied to V
CC
and V
CCQ
simultaneously, and
then to V
REF
(and to the system V
TT
). V
TT
must be applied
after V
CCQ
to avoid device latch-up, which may cause
permanent damage to the device. V
REF
can be applied any
time after V
CCQ
but is expected to be nominally coincident
with V
TT
. Except for CKE, inputs are not recognized as
valid until after VREF is applied. CKE is an SSTL_2
input but will detect an LVCMOS LOW level after V
CC
is
applied. After CKE passes through V
IH
, it will transition to
an SSTL_2 signal and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior
to applying an executable command.
Once the 200µs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the D
LL
, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the D
LL
and to program the operating
parameters. Two-hundred clock cy cles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (t
RFC
must be satisfied.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
pa ram e ters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
V
REF
A
0-12
BA
0-1
CK
0
CK
0
#
CKE
0
CS
0
#
DQML
0
DQMH
0
DQSL
0
DQSH
0
BA
0-1
CK
CK#
CKE
CS#
DQML
DQMH
DQSL
DQSH
U0
WE
1
#
RAS
1
#
CAS
1
#
WE# RAS# CAS#
V
REF
A
0-12
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
16
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
31
CK
1
CK
1
#
CKE
1
CS
1
#
DQML
1
DQMH
1
DQSL
1
DQSH
1
BA
0-1
CK
CK#
CKE
CS#
DQML
DQMH
DQSL
DQSH
U1
WE
2
#
RAS
2
#
CAS
2
#
WE# RAS# CAS#
V
REF
A
0-12
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
32
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
47
CK
2
#
CK
2
#
CKE
2
CS
2
#
DQML
2
DQMH
2
DQSL
2
DQSH
2
BA
0-1
CK
CK#
CKE
CS#
DQML
DQMH
DQSL
DQSH
U2
WE
3
#
RAS
3
#
CAS
3
#
WE# RAS# CAS#
V
REF
A
0-12
CK
3
CK
3
#
CKE
3
CS
3
#
DQML
3
DQMH
3
DQSL
3
DQSH
3
BA
0-1
CK
CK#
CKE
CS#
DQML
DQMH
DQSL
DQSH
U3
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
48
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
63
WE
4
#
RAS
4
#
CAS
4
#
WE# RAS# CAS#
V
REF
A
0-12
CK
4
CK
4
#
CKE
4
CS
4
#
DQML
4
DQMH
4
DQSL
4
DQSH
4
BA
0-1
CK
CK#
CKE
CS#
DQML
DQMH
DQSL
DQSH
U4
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
64
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
79
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2006
Rev. 6
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
and an operating mode, as shown in Figure 3. The Mode
Register is programmed via the MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored information until it is programmed again or
the device loses power. (Except for bit A8 which is self
clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must
wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result
in unspecified operation.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the
operating mode.
W3E32M72S-XSBX
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
READ LATENCY
The READ latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first bit of output data. The latency can be set to 2
or 2.5 clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to
zero, and bits A0-A6 set to the desired values. A DLL reset
is initiated by issuing a MODE REGISTER SET command
with bits A7 and A9-A12 each set to zero, bit A8 set to one,
and bits A0-A6 set to the desired values. Although not
required, JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGISTER
command to select normal operating mode.
All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable,
as shown in Fig ure 3. The burst length determines
the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-Ai when the burst length is set to two; by A2-Ai when the
burst length is set to four (where Ai is the most significant
column address for a given configuration); and by A3-Ai
when the burst length is set to eight. The remaining (least
significant) address bit(s) is (are) used to select the starting
location within the block. The programmed burst length
applies to both READ and WRITE bursts.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
and QFC. These functions are controlled via the bits shown
in Figure 5. The extended mode register is programmed
via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2006
Rev. 6
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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