W29C102
64K
×
16 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W29C102 is a 1-megabit, 5-volt only CMOS flash memory organized as 64K
×
16 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V
PP
is
not required. The unique cell architecture of the W29C102 results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
•
Single 5-volt program and erase operations
•
Fast page-write operations
•
Low power consumption
−
128 words per page
−
Page program cycle: 10 mS (max.)
−
Effective word-program cycle time: 39
µS
−
Optional software-protected data write
•
Fast chip-erase operation: 50 mS
•
Read access time: 70/90/120 nS
•
Typical page program/erase cycles: 1K/10K
•
Ten-year data retention
•
Software and hardware data protection
−
Active current: 25 mA (typ.)
−
Standby current: 20
µA
(typ.)
•
Automatic program timing with internal V
PP
generation
•
End of program detection
−
Toggle bit
−
Data polling
•
Latched address and data
•
TTL compatible I/O
•
JEDEC standard word-wide pinouts
•
Available packages: 40-pin 600 mil DIP, TSOP
and 44-pin PLCC
-1-
Publication Release Date: March 1998
Revision A3
W29C102
PIN CONFIGURATIONS
NC
CE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
GND
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
BLOCK DIAGRAM
V
DD
WE
NC
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
V
DD
V
SS
CE
OE
WE
CONTROL
OUTPUT
BUFFER
40-pin
DIP
32
31
30
29
28
27
26
25
24
23
22
21
DQ0
.
.
DQ15
A0
A9
A10
A11
A12
A13
A14
A15
NC
WE
V
DD
NC
CE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
40-pin
TSOP
32
31
30
29
28
27
26
25
24
23
22
21
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
GND
.
.
A15
DECODER
CORE
ARRAY
PIN DESCRIPTION
D D D /
Q Q Q C N N
13 14 15 E C C
6
5
4
3
2
1
V
D
D
/
W N
E C
A A
1 1
5 4
SYMBOL
39
38
37
36
PIN NAME
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
44 43 42 41 40
DQ12
DQ11
DQ10
DQ9
DQ8
GND
NC
DQ7
DQ6
DQ5
DQ4
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
A0−A15
DQ0−DQ15
CE
OE
WE
V
DD
GND
NC
44-pin
PLCC
35
34
33
32
31
30
29
D D D D
Q Q Q Q
3 2 1 0
/ N A A
O C 0 1
E
A A A
2 3 4
-2-
W29C102
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29C102 is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.
Refer to the timing waveforms for further details.
Page Write Mode
The W29C102 is programmed on a page basis. Every page contains 128 words of data. If a word of
data within a page is to be changed, data for the entire page must be loaded into the device. Any
word that is not loaded will be erased to "FFh" during programming of the page.
The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists
of two steps. Step 1 is the word-load cycle, in which the host writes to the page buffer of the device.
Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously
written into the memory array for non-volatile storage.
During the word-load cycle, the addresses are latched by the falling edge of either CE or WE,
whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs
first. If the host loads a second word into the page buffer within a word-load cycle time (T
BLC
) of 200
µS,
after the initial word-load cycle, the W29C102 will stay in the page load cycle. Additional words
can then be loaded consecutively. The page load cycle will be terminated and the internal
programming cycle will start if no additional word is loaded into the page buffer. A
7
to A1
5
specify the
page address. All words that are loaded into the page buffer must have the same page address. A
0
to
A
6
specify the word address within the page. The words may be loaded in any order; sequential
loading is not required.
In the internal programming cycle, all data in the page buffers, i.e., 128 words of data, are written
simultaneously into the memory array. The typical programming time is 5 mS. The entire memory
array can be written in 2.6 seconds. Before the completion of the internal programming cycle, the host
is free to perform other tasks such as fetching data from other locations in the system to prepare to
write the next page.
Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a series of three-word program commands (with specific data to
a specific address) to be performed before the data load operation. The three-word load command
sequence begins the page load cycle, without which the write operation will not be activated. This
write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by
noise during system power-up and power-down.
The W29C102 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-word command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-word program command cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the
-3-
Publication Release Date: March 1998
Revision A3
W29C102
software data protection feature. To reset the device to unprotected mode, a six-word command
sequence is required. See Table 3 for specific codes and Figure 10 for the timing diagram.
Hardware Data Protection
The integrity of the data stored in the W29C102 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) V
DD
Power Up/Down Detection: The programming operation is inhibited when V
DD
is less than
2.5V.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) V
DD
power-on delay: When V
DD
has reached its sense level, the device will automatically time-out
5 mS before any write (erase/program) operation.
Data Polling (DQ
7 &
DQ
15
)- Write Status Detection
The W29C102 includes a data polling feature to indicate the end of a programming cycle. When the
W29C102 is in the internal programming cycle, any attempt to read DQ
7
and/or DQ
15
of the last word
loaded during the page/word-load cycle will receive the complement of the true data. Once the
programming cycle is completed. DQ
7
will show the true data.
Toggle Bit (DQ
6
& DQ
14
)- Write Status Detection
In addition to data polling, the W29C102 provides another method for determining the end of a
program cycle. During the internal programming cycle, any consecutive attempts to read DQ
6
and/or
DQ
14
will produce alternating 0's and 1's. When the programming cycle is completed, this toggling
between 0's and 1's will stop. The device is then ready for the next operation.
5-Volt-only Software Chip Erase
The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycles, the device enters the internal chip erase mode, which is automatically timed and will be
completed in 50 mS. The host system is not required to provide any control or timing during this
operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-word command sequence can be used to access the product ID. A read
from address 0000H outputs the manufacturer code (00DAh). A read from address 0001H outputs the
device code (004Fh). The product ID operation can be terminated by a three-word command
sequence.
In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE
high, and raising A9 to 12 volts.
-4-
W29C102
TABLE OF OPERATING MODES
Operating Mode Selection
(V
HH
= 12V)
MODE
CE
Read
Write
Standby
Write Inhibit
Output Disable
5-Volt Software Chip Erase
Product ID
V
IL
V
IL
V
IH
X
X
X
V
IL
V
IL
V
IL
OE
V
IL
V
IH
X
V
IL
X
V
IH
V
IH
V
IL
V
IL
WE
V
IH
V
IL
X
X
V
IH
X
V
IL
V
IH
V
IH
A
IN
A
IN
X
X
X
X
A
IN
PINS
ADDRESS
Dout
Din
High Z
High Z/D
OUT
High Z/D
OUT
High Z
D
IN
Manufacturer Code
00DA (Hex)
Device Code
004F (Hex)
DQ.
A0 = V
IL
; A1−A15 = V
IL
;
A9 = V
HH
A0 = V
IH
; A1−A15 = V
IL
;
A9 = V
HH
-5-
Publication Release Date: March 1998
Revision A3
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