áç
NOVEMBER 2001
XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
GENERAL DESCRIPTION
The XRT81L27 is an optimized seven-channel, ana-
log, 3.3V, line interface unit, fabricated using low pow-
er CMOS technology. The device contains seven in-
dependent E1 channels, including data and clock re-
covery circuits. It is primarily targeted towards the
SDH multiplexers that accommodate TU12 Tributary
Unit Frames. Line cards in these units multiplex 21 E1
channels into higher SDH rates. Devices with seven
E1 interfaces such as the XRT81L27 provide the
most efficient method of implementing 21-channel
line cards. Each channel performs the driver and re-
ceiver functions necessary to convert bipolar signals
to logical levels and vice versa.
The receiver input accepts transformer or capacitor
coupled signals, while the transmitter is coupled to
the line using a 1:2 step-up transformer. The same
transformer configuration can be used for both bal-
anced 120
Ω
and unbalanced 75
Ω
interfaces. The
Receiver Loss of Original Detection is compliant to
G.775 and in Host Mode, the number of zeros re-
ceived before RLOS is declared can be increased to
4096 bits. This feature provides the user with the flex-
ibility to implement RLOS specifications that require
greater than G.775 requirements
F
IGURE
1. B
LOCK
D
IAGRAM
SDO
SDI
SClk
CS
RST
LBM
LBEN
SR/DR
MODE
RClkP
ICT
MCLK
TClkP
TPOS_n
TCLK_n
TNEG_n
PDTx_n
TAOS_n
RClkP
Remote
Loopback
LOS
Detect
TCLKP
Encoded
PDATA
MCLK
FEATURES
•
Seven (7) Independent E1 (CEPT) Line Interface
Units (Transmitter, Receiver, and Recovery)
•
Transmit Output Pulses that are Compliant with the
ITU-T G.703 Pulse Template Requirement for
2.048Mbps (E1) Rates
•
On-Chip Pulse Shaping for both 75Ω and 120Ω line
drivers
•
Receiver Can Either Be Transformer or Capacitive-
Coupled to the Line
•
Detects and Clears LOS (Loss of Signal) Per ITU-T
G.775 and ETS 300 233 (programmable from Host)
•
Compliant with the ITU-T G.823 Jitter Tolerance
Requirements
•
3.3V operation with 5V Input compatibility
•
Low power consumption
APPLICATIONS
•
SDH and lPDH Multiplexers
•
E1 Digital Cross-Connect Systems
•
DECT (Digital European Cordless Telephone) Base
Stations
•
CSU/DSU Equipment
Microprocessor
Serial
Interface
(MSI)
Channel 6
Channel 5
Channel 4
Global
Control
Channel 3
Channel 2
Channel 1
Channel 0
Timing
Control
MUX
Timing
Control
TX
Pulse
Shaper
TTIP_n
Line
Driver
TRING_n
Encoder
Encoded
NDATA
Digital
Loopback
LOS_n
Analog
Loopback
RPOS_n
RClk_n
RNEG_n
Decoder
Data & Timing
Recovery
MUX
Peak
Detector
Receive
Equalizer
RTIP_n
RRING_n
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
áç
F
IGURE
2. P
IN
O
UT OF THE
XRT81L27
RPOS_3/RDATA_3
RNEG_3/LCV_3
RClk_3
LOS_3
RPOS_1/RDATA_1
RNEG_1/LCV_1
RClk_1
LOS_1
ICT
RTIP_1
RRing_1
PDTx_1
TTIP_1
TVDD_1
TRing_1
TGND_1
PDTx_3
TTIP_3
TVDD_3
TRing_3
TGND_3
AVDD
RTIP_3
RRing_3
AGND
RTIP_5
RRing_5
PDTx_5
TTIP_5
TVDD_5
TRing_5
TGND_5
MCLK
SR/DR
RTIP_6
RRing_6
TClkP
RClkP
AVDD
AGND
TClk_1
TPOS_1/TDATA_1
TNEG_1/CODE_1
TAOS_1
TClk_3
TPOS_3/TDATA_3
TNEG_3/CODE_3
TAOS_3
TAOS_2
TNEG_2/CODE_2
TPOS_2/TDATA_2
TClk_2
TAOS_0
TNEG_0/CODE_0
TPOS_0/TDATA_0
TClk_0
GND
VDD
RPOS_2/RDATA_2
RNEG_2/LCV_2
RClk_2
LOS_2
RPOS_0/RDATA_0
RNEG_0/LCV_0
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
XRT81L27
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
RClk_6
RNEG_6/LCV_6
RPOS_6/RDATA_6
LOS_6
RClk_5
RNEG_5/LCV_5
RPOS_5/RATA_5
LOS_5
VDD
GND
TxClk_5
TPOS_5/TDATA_5
TNEG_5/CODE_5
TAOS_5
CS/B3
SClk/B2
SDI/B1
SDO/LBM
TAOS_6
TNEG_6/CODE_6
TPOS_6/TDATA_6
TClk_6
GND
VDD
TAOS_4
TNEG_4/CODE_4
P
ART
N
UMBER
XRT81L27IV
RClk_0
LOS_0
RST/LBEN
RTIP_0
RRing_0
PDTx_0
TTIP_0
TVDD_0
TRing_0
TGND_0
PDTx_2
TTIP_2
TVDD_2
TRing_2
TGND_2
AVDD
RTIP_2
RRing_2
AGND
RTIP_4
RRing_4
PDTx_4
TTIP_4
TVDD_4
TRing_4
TGND_4
PDTx_6
TTIP_6
TVDD_6
TRing_6
TGND_6
MODE
RClk_4
RNEG_4/LCV_4
RPOS_4/RDATA_4
LOS_4
TClk_4
TPOS_4/TDATA_4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
ORDERING INFORMATION
P
ACKAGE
128 Lead TQFP
O
PERATING
T
EMPERATURE
R
ANGE
-40
°
C to +85
°
C
2
áç
XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................. 1
F
EATURES
...................................................................................................................................................
A
PPLICATIONS
..............................................................................................................................................
Figure 1. Block Diagram ...................................................................................................................
Figure 2. Pin Out of the XRT81L27 ...................................................................................................
ORDERING INFORMATION ...............................................................................................................
1
1
1
2
2
TABLE OF CONTENTS ....................................................................................................... I
PIN DESCRIPTIONS ........................................................................................................... 3
T
ABLE
1: P
IN
N
UMBER BY
P
IN
N
AME
..................................................................................................... 9
ELECTRICAL CHARACTERISTICS ................................................................................. 10
T
ABLE
2: A
BSOLUTE
M
AXIMUM
R
ATINGS
............................................................................................. 10
T
ABLE
3: DC E
LECTRICAL
C
HARACTERISTICS
..................................................................................... 10
T
ABLE
4: T
RANSMITTER
E
LECTRICAL
C
HARACTERISTICS
...................................................................... 10
T
ABLE
5: P
ER
C
HANNEL
P
OWER
C
ONSUMPTION INCLUDING LINE POWER DISSIPATION
,
TRANSMISSION AND
RECEIVE PATHS ALL ACTIVE
.................................................................................................... 11
T
ABLE
6: R
ECEIVER
E
LECTRICAL
C
HARACTERISTICS
........................................................................... 11
Figure 3. Receive Output Timing ................................................................................................... 12
Figure 4. Transmit Input Timing ..................................................................................................... 12
T
ABLE
7: AC E
LECTRICAL
C
HARACTERISTICS
..................................................................................... 12
T
HE
H
ARDWARE MODE
............................................................................................................................... 13
T
HE
H
OST
M
ODE
....................................................................................................................................... 13
1.0 The Microprocessor Serial Interface (MSI) ........................................................................................... 13
1.1 M
ICROPROCESSOR
S
ERIAL
I
NTERFACE DESCRIPTION
. ............................................................................ 13
U
SING THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
(MSI) ............................................................................ 13
1.1.1 Selection Phase ........................................................................................................................ 13
1.1.2 Data phase of the (MSI) operation ........................................................................................... 14
Figure 5. Timing Diagram for the Microprocessor Serial Interface ............................................ 14
T
ABLE
8: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMING
(
SEE
F
IGURE
5) ............................................. 15
Figure 6. Microprocessor Serial Interface Data Structure ........................................................... 15
1.2 D
ESCRIPTION OF THE
C
OMMAND
R
EGISTERS
........................................................................................ 16
T
ABLE
9: M
ICROPROCESSOR
R
EGISTER
A
DDRESS AND
C
ONTROL
........................................................ 16
T
ABLE
10: C
OMMAND
C
ONTROL
R
EGISTER
- A
DDRESS
0000 - HEX 0
X
00 ........................................... 16
(C
OMMON TO ALL
S
EVEN
C
HANNELS
) ............................................................................................ 16
T
ABLE
11: L
OCAL
L
OOP
-
BACK
R
EGISTERS
- A
DDRESS
: 0001, HEX 0
X
01 ........................................... 17
T
ABLE
12: R
EMOTE
L
OOP
-
BACK
R
EGISTERS
- A
DDRESS
: 0010, HEX 0
X
02 ......................................... 17
T
ABLE
13: A
NALOG
L
OOP
-
BACK
R
EGISTERS
- A
DDRESS
: 0011, HEX 0
X
03 ......................................... 17
T
ABLE
14: TAOS R
EGISTERS
- A
DDRESS
: 0100, HEX 0
X
04 ............................................................... 17
T
ABLE
15: RAOS R
EGISTERS
- A
DDRESS
: 0101, HEX 0
X
05 ............................................................... 17
T
ABLE
16: PDT
X
R
EGISTERS
- A
DDRESS
: 0110, HEX 0
X
06 ................................................................ 18
1.3 O
PERATION OF THE
C
OMMAND
C
ONTROL
R
EGISTER BITS
(A
DDRESS
: 0000, HEX 0
X
00) ........................ 18
TC
LK
P (
BIT
0) ............................................................................................................................................ 18
RC
LK
P (
BIT
1) ........................................................................................................................................... 18
CODE (
BIT
2) ............................................................................................................................................ 18
SR/DR (
BIT
3) ........................................................................................................................................... 18
MUTE (
BIT
4) ............................................................................................................................................ 18
EXLOS (
BIT
5) .......................................................................................................................................... 18
ARAOS (
BIT
6) .......................................................................................................................................... 18
1.4 C
HANNEL
C
ONTROL
R
EGISTERS
........................................................................................................... 18
LLB[6:0] (
ADDRESS
0001) ......................................................................................................................... 18
RLB[6:0] (
ADDRESS
0010) ......................................................................................................................... 18
ALB
X
(
ADDRESS
0011) .............................................................................................................................. 18
TAOS[6:0] (
ADDRESS
0100) ...................................................................................................................... 18
I
XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
áç
RAOS[6:0] (
ADDRESS
0101) ...................................................................................................................... 18
PDTX[6:0] (
ADDRESS
0110) ....................................................................................................................... 18
2.0 The transmit section ............................................................................................................................... 19
2.1 T
HE
T
RANSMIT
L
OGIC
B
LOCK
. ............................................................................................................... 19
Figure 7. The Interface for the Transmission of Data From the Transmitting Terminal Equipment
to the Transmit Section of the XRT81L27 ......................................................................... 19
2.1.1 Dual-rail input mode .................................................................................................................. 19
Figure 8. Dual Rail Data from the Terminal .................................................................................... 19
2.1.2 Single-rail input mode ............................................................................................................... 19
Figure 9. Single-Rail Data From the Terminal ............................................................................... 20
2.1.3 TClk input .................................................................................................................................. 20
2.2 T
HE
E
NCODER BLOCK
........................................................................................................................... 20
2.2.1 HDB3 Encoding ......................................................................................................................... 20
Figure 10. HDB3 Encoding .............................................................................................................. 20
2.3 T
HE
MUX
BLOCK
.................................................................................................................................. 20
2.3.1 Timing Control Block ................................................................................................................. 21
2.3.2 The Transmit Clock Duty Cycle Adjust Circuit .......................................................................... 21
2.3.3 Transmit All Ones ...................................................................................................................... 21
2.4 T
HE
P
ULSE
S
HAPING
C
IRCUIT
............................................................................................................... 21
Figure 11. ITU-T G.703 Pulse Template .......................................................................................... 22
2.5 T
HE
L
INE
D
RIVER BLOCK
...................................................................................................................... 22
2.6 I
NTERFACING THE
T
RANSMIT
S
ECTIONS OF THE
XRT81L27
TO THE
L
INE
............................................... 22
Figure 12. Illustration of how to interface the Transmit Sections of the XRT81L27 to the Line (for
75 or 120W Applications) ................................................................................................... 23
3.0 The Receive Section ............................................................................................................................... 23
3.1 I
NTERFACING THE
R
ECEIVE
S
ECTIONS TO THE
L
INE
............................................................................... 23
Figure 13. Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 75W
(Transformer-Coupled) Applications ................................................................................ 24
Figure 14. Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 120W
(Transformer-Coupled) Applications ................................................................................ 24
3.2 C
APACITIVE
-C
OUPLING THE
R
ECEIVER TO THE
L
INE
............................................................................... 25
Figure 15. Capacitive - Coupled Receive Sections of the XRT81L27 to the Line (for Balanced
120W Applications) ............................................................................................................. 25
3.3 T
HE
R
ECEIVE
E
QUALIZER
B
OCK
............................................................................................................ 25
3.4 T
HE
P
EAK
D
ETECTOR AND
S
LICER
B
LOCK
............................................................................................. 26
3.5 T
HE
LOS D
ETECTOR BLOCK
................................................................................................................. 26
Figure 16. Package Outline Drawing .............................................................................................. 27
R
EVISIONS
................................................................................................................................................. 28
II
áç
XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
PIN DESCRIPTIONS
N
OTE
: I -H
indicates an input pin with a 50kΩ pull-up Resistor, I-L indicates an input pin with a 50kΩ pull-down resistor.
P
IN
#
1
2
N
AME
RClk_0
LOS_0
T
YPE
O
O
Receiver 0 Clock Output
Receiver 0 Loss of Signal:
This signal is asserted "High" to indicate loss of signal at the receive
input.
Reset (Active-low): (Host Mode)
“Low” Resets the register contents to zero.
Loop-back Enable (Active-low): (Hardware Mode)
“Low” for Loop-back mode enable.
Receiver 0 Bipolar Positive Input:
Receiver 0 Bipolar Negative Input:
Power-down Transmitter 0:
This pin is operational for both
Host
or
Hardware Mode.
This pin MUST be pulled “Low” to enable TTIP_0 and TRING_0 output
buffers.
Pull this pin "High" to power-down channel 0 transmitter and set TTIP_0
and TRING_0 outputs to high impedance.
Transmitter 0 Tip Output:
Positive bipolar data output to the line
Transmitter 0 Positive Supply (3.3V± 5%)
Transmitter 0 Ring Output:
Negative bipolar data output to the line.
Transmitter 0 Supply Ground
Power-down Transmitter 2:
(see pin 6)
Transmitter 2 Tip Output:
Positive bipolar data output to the line.
Transmitter 2 Positive Supply(3.3V± 5%)
Transmitter 2 Ring Output:
Negative bipolar data output to the line.
Transmitter 2 Supply Ground.
Analog Positive Supply(3.3V± 5%)
Receiver 2 Bipolar Positive Input:
Receiver 2 Bipolar Negative Input:
Analog Supply Ground.
Receiver 4 Bipolar Positive Input:
Receiver 4 Bipolar Negative Input:
Power-down Transmitter 4:
(see pin 6)
Transmitter 4 Tip Output:
Positive bipolar data output to the line.
Transmitter 4 Positive Supply(3.3V± 5%)
Transmitter 4 Ring Output:
Negative bipolar data output to the line.
D
ESCRIPTION
3
RST
I-H
LBEN
4
5
6
RTIP_0
RRING_0
PDTx_0
I
I
I-H
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TTIP_0
TVDD_0
TRING_0
TGND_0
PDTx_2
TTIP_2
TVDD_2
TRING_2
TGND_2
AVDD
RTIP_2
RRING_2
AGND
RTIP_4
RRING_4
PDTx_4
TTIP_4
TVDD_4
TRING_4
O
Vdd
O
Gnd
I-H
O
Vdd
O
Gnd
AVdd
I
I
Gnd
I
I
I-H
O
Vdd
O
3
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