JUNE 2007
Rev. 1.0.2
XRT91L30
STS-12/STM-4 or STS-3/STM-1 SONET/SDH TRANSCEIVER
Network & Transmission Products
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.2
NOTES:
II
XRT91L30
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
TABLE OF CONTENTS
NOTES:..................................................................................................................................................... II
T
ABLE OF
C
ONTENTS
............................................................................................................
I
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS........................................................................................................................................... 1
F
IGURE
1. B
LOCK
D
IAGRAM OF
XRT91L30 ...................................................................................................................................... 1
FEATURES
..................................................................................................................................................... 2
F
IGURE
2. 64 QFP P
IN
O
UT OF THE
XRT91L30 (T
OP
V
IEW
)............................................................................................................ 3
ORDERING INFORMATION .................................................................................................................... 3
T
ABLE
1: ........................................................................................................................................................................................ 4
PIN DESCRIPTIONS .......................................................................................................... 4
..................................................................................................................................................................... 4
H
ARDWARE
C
ONTROL
.................................................................................................................................... 4
T
RANSMITTER
S
ECTION
.................................................................................................................................. 7
R
ECEIVER
S
ECTION
....................................................................................................................................... 9
P
OWER AND
G
ROUND
.................................................................................................................................. 10
1.0 FUNCTIONAL DESCRIPTION ............................................................................................................. 12
1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 12
1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 12
T
ABLE
2: CMU R
EFERENCE
F
REQUENCY
O
PTIONS
(D
IFFERENTIAL OR
S
INGLE
-E
NDED
) ................................................................... 12
1.3 DATA LATENCY ............................................................................................................................................. 12
T
ABLE
3: D
ATA INGRESS TO DATA EGRESS LATENCY
....................................................................................................................... 12
2.0 RECEIVE SECTION ............................................................................................................................. 13
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 13
F
IGURE
3. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
B
LOCK
..................................................................................................................... 13
2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 14
F
IGURE
4. R
ECEIVE
H
IGH
-S
PEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
D
IAGRAM
.......................................................................................... 14
T
ABLE
4: R
ECEIVE
H
IGH
-
SPEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
) ............................................................. 14
T
ABLE
5: R
ECEIVE
H
IGH
-S
PEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
)............................................................... 14
2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15
T
ABLE
6: C
LOCK
D
ATA
R
ECOVERY UNIT REFERENCE CLOCK SETTINGS
............................................................................................ 15
T
ABLE
7: C
LOCK AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
.......................................................................................................... 15
2.3.1 INTERNAL CLOCK AND DATA RECOVERY BYPASS ............................................................................................ 16
F
IGURE
5. I
NTERNAL
C
LOCK AND
D
ATA
R
ECOVERY
B
YPASS
............................................................................................................ 16
2.4 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 16
F
IGURE
6. E
XTERNAL
L
OOP
F
ILTERS
.............................................................................................................................................. 16
2.5 LOSS OF SIGNAL .......................................................................................................................................... 16
F
IGURE
7. LOS D
ECLARATION CIRCUIT
........................................................................................................................................... 17
2.6 SONET FRAME BOUNDARY DETECTION AND BYTE ALIGNMENT RECOVERY .................................... 17
2.7 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 17
F
IGURE
8. S
IMPLIFIED
B
LOCK
D
IAGRAM OF
SIPO ........................................................................................................................... 18
2.8 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 18
F
IGURE
9. R
ECEIVE
P
ARALLEL
O
UTPUT
I
NTERFACE
B
LOCK
............................................................................................................. 18
2.9 DISABLE PARALLEL RECEIVE DATA OUTPUT UPON LOS ..................................................................... 18
2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 19
F
IGURE
10. R
ECEIVE
P
ARALLEL
O
UTPUT
T
IMING
............................................................................................................................ 19
T
ABLE
8: R
ECEIVE
P
ARALLEL
D
ATA
O
UTPUT
T
IMING
(STS-12/STM-4 O
PERATION
) ......................................................................... 19
T
ABLE
9: R
ECEIVE
P
ARALLEL
D
ATA
O
UTPUT
T
IMING
(STS-3/STM-1 O
PERATION
) ........................................................................... 19
T
ABLE
10: PECL
AND
TTL R
ECEIVE
O
UTPUTS
T
IMING
S
PECIFICATION
............................................................................................ 20
3.0 TRANSMIT SECTION .......................................................................................................................... 21
3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................ 21
F
IGURE
11. T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
............................................................................................................. 21
3.2 TRANSMIT PARALLEL DATA INPUT TIMING ............................................................................................. 22
F
IGURE
12. T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
.............................................................................................................................. 22
T
ABLE
11: T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
)......................................................................... 22
T
ABLE
12: T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
)........................................................................... 22
3.3 ALTERNATE TRANSMIT PARALLEL BUS CLOCK INPUT OPTION .......................................................... 23
F
IGURE
13. A
LTERNATE
T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
(P
ARALLEL
C
LOCK
I
NPUT
O
PTION
) ...................................... 23
3.4 ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING ....................................................................... 23
I
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.2
F
IGURE
14. A
LTERNATE
T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
............................................................................................................ 23
T
ABLE
13: A
LTERNATE
T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
) ...................................................... 24
T
ABLE
14: A
LTERNATE
T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
). ....................................................... 24
3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 24
F
IGURE
15. S
IMPLIFIED
B
LOCK
D
IAGRAM OF
PISO ......................................................................................................................... 24
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 25
T
ABLE
15: C
LOCK
M
ULTIPLIER
U
NIT
’
S
R
EQUIREMENTS FOR
R
EFCLK
................................................................................................ 25
3.7 LOOP TIMING AND CLOCK CONTROL ........................................................................................................ 25
T
ABLE
16: L
OOP
T
IMING AND
C
LOCK
R
ECOVERY CONFIGURATIONS
................................................................................................. 26
F
IGURE
16. L
OOP
T
IMING
M
ODE
U
SING
I
NTERNAL
CDR
OR AN
E
XTERNAL
R
ECOVERED
C
LOCK
....................................................... 26
3.8 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 27
F
IGURE
17. T
RANSMIT
S
ERIAL
O
UTPUT
I
NTERFACE BLOCK
.............................................................................................................. 27
4.0 DIAGNOSTIC FEATURES ...................................................................................................................28
4.1 SERIAL REMOTE LOOPBACK ...................................................................................................................... 28
F
IGURE
18. S
ERIAL
R
EMOTE
L
OOPBACK
......................................................................................................................................... 28
4.2 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 28
F
IGURE
19. D
IGITAL
L
OCAL
L
OOPBACK
........................................................................................................................................... 28
4.3 ANALOG LOCAL LOOPBACK ...................................................................................................................... 29
F
IGURE
20. A
NALOG
L
OCAL
L
OOPBACK
.......................................................................................................................................... 29
4.4 SPLIT LOOPBACK ......................................................................................................................................... 29
F
IGURE
21. S
PLIT
L
OOPBACK
......................................................................................................................................................... 29
4.5 EYE DIAGRAM ............................................................................................................................................... 30
F
IGURE
22. T
RANSMIT
E
LECTRICAL
O
UTPUT
E
YE
D
IAGRAM
............................................................................................................. 30
4.6 SONET JITTER REQUIREMENTS ................................................................................................................. 30
4.6.1 JITTER TOLERANCE: ................................................................................................................................................ 30
F
IGURE
23. GR-253 J
ITTER
T
OLERANCE
M
ASK
.............................................................................................................................. 31
T
ABLE
17: XRT91L30 R
ECEIVER
J
ITTER
T
OLERANCE
P
ERFORMANCE
............................................................................................. 31
F
IGURE
24. XRT91L30 M
EASURED
J
ITTER
T
OLERANCE WITH
77.76MH
Z
R
EFERENCE
C
LOCK
......................................................... 31
F
IGURE
25. XRT91L30 M
EASURED
J
ITTER
T
OLERANCE WITH
19.44MH
Z
R
EFERENCE
C
LOCK
......................................................... 32
4.6.2 JITTER GENERATION................................................................................................................................................ 32
T
ABLE
18: XRT91L30 O
PTICAL
J
ITTER
G
ENERATION USING
223-1 PRBS
PATTERN
........................................................................ 32
T
ABLE
19: XRT91L30 O
PTICAL
J
ITTER
G
ENERATION USING
223-1 PRBS
PATTERN USING ALTERNATE STANDARD
F
ILTERS
.............. 32
5.0 ELECTRICAL CHARACTERISTICS ....................................................................................................33
A
BSOLUTE
M
AXIMUM
RATINGS...................................................................................................................33
ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS ..........................................................33
POWER AND CURRENT DC E
LECTRICAL
C
HARACTERISTICS
....................................................................33
...................................................................................................................................................................33
LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS ......................................34
ORDERING INFORMATION...................................................................................................................35
PACKAGE DIMENSIONS.................................................................................................35
R
EVISION
H
ISTORY
.......................................................................................................................................36
II
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
MAY 2007
REV. 1.0.2
GENERAL DESCRIPTION
The XRT91L30 is a fully integrated SONET/SDH
transceiver for SONET/SDH 622.08 Mbps STS-12/
STM-4 or 155.52 Mbps STS-3/STM-1 applications.
The transceiver includes an on-chip Clock Multiplier
Unit (CMU), which uses a high frequency Phase-
Locked Loop (PLL) to generate the high-speed
transmit serial clock from a slower external clock
reference. It also provides Clock and Data Recovery
(CDR) function by synchronizing its on-chip Voltage
Controlled Oscillator (VCO) to the incoming serial
data stream. The internal CDR unit can be disabled
and bypassed in lieu of an externally recovered
received clock from the optical module. Either the
internally recovered clock or the externally recovered
clock can be used for loop timing applications. The
chip provides serial-to-parallel and parallel-to-serial
converters using an 8-bit wide LVTTL system
interface in both receive and transmit directions.
The transmit section includes an option to accept a
parallel clock signal from the framer/mapper to
F
IGURE
1. B
LOCK
D
IAGRAM OF
XRT91L30
synchronize the transmit section timing. The device
can internally monitor Loss of Signal (LOS) condition
and automatically mute received data upon LOS. An
on-chip SONET/SDH frame byte and boundary
detector and frame pulse generator offers the ability
recover SONET/SDH framing and to byte align the
receive serial data stream into the 8-bit parallel bus.
APPLICATIONS
•
SONET/SDH-based Transmission Systems
•
Add/Drop Multiplexers
•
Cross Connect Equipment
•
ATM and Multi-Service Switches, Routers and
Switch/Routers
•
DSLAMS
•
SONET/SDH Test Equipment
•
DWDM Termination Equipment
STS-12/STM-4 or STS-3/STM-1
TRANSCEIVER
TXDI[7:0]
8
TXPCLK_IO
REFCLKP/N
TTLREFCLK
PISO
(Parallel Input
Serial Output)
ENB
Re-Timer
TXOP/N
MUX
Div by
8
ENB
XOR
CMU
DLOOP
RLOOPS
ALOOP
MUX
CDRAUXREFCLK
MUX
RXDO[7:0]
SIPO
(Serial Input
Parallel Output)
CDR
MUX
RXIP/N
8
XRXCLKIP/N
RXPCLKO
Div by 8
Control Block
Loop Filters
Clock Control
CAP1N
CAP2N
CAP1P
CAP2P
DLOSDIS
LOSEXT
OOF
FRAMEPULSE
CDRDIS
CMUFREQSEL
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
STS-12/STS-3
CDRREFSEL
LOOPTIME
PIO_CTRL
RLOOPS
DLOOP
ALOOP
Reset
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