XR16V2650
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
MAY 2007
REV. 1.0.2
GENERAL DESCRIPTION
The XR16V2650
1
(V2650) is a high performance dual
universal asynchronous receiver and transmitter
(UART) with 32 bytes TX and RX FIFOs. The device
operates from 2.25 to 3.6 volts with 5 Volt tolerant
inputs and is pin-to-pin compatible to Exar’s
ST16C2550, XR16C2550 and XR16V2550. The
V2650 register set is compatible to the ST16C2550,
the XR16L2550 and the XR16V2550. It supports
Exar’s enhanced features of selectable FIFO trigger
level, automatic hardware (RTS/CTS) and software
flow control, and a complete modem interface.
Onboard registers provide the user with operational
status and data error flags. An internal loopback
capability allows system diagnostics. Independent
programmable baud rate generators are provided in
each channel to select data rates up to 16 Mbps at
3.3 Volt with 4X sampling clock. The V2650 is
available in 48-pin TQFP and 32-pin QFN packages.
N
OTE
:
1 Covered by U.S. Patent #5,649,122
FEATURES
•
2.25 to 3.6 Volt Operation
•
5 Volt Tolerant Inputs
•
Pin-to-pin compatible to ST16C2550, XR16C2550,
XR16L2550 and XR16V2550 in the 48-TQFP
package
•
Two independent UART channels
■
■
Register set compatible to XR16V2550
Data rate of up to
16 Mbps at 3.3 V,
and
12.5
Mbps at 2.5 V
with 4X sampling rate
Fractional Baud Rate Generator
Transmit and Receive FIFOs of 32 bytes
Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Automatic sleep mode
Full modem interface
■
■
■
■
■
■
■
■
APPLICATIONS
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. XR16V2650 B
LOCK
D
IAGRAM
•
Device Identification and Revision
•
Crystal oscillator (up to 32MHz) or external clock
(up to 64MHz) input
•
48-TQFP and 32-QFN packages
* 5 Volt Tolerant Inputs
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
INTA
INTB
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
Reset
8-bit Data
Bus
Interface
UART Channel A
UART
Regs
BRG
32 Byte TX FIFO
TX & RX
IR
ENDEC
2.25 to 3.6 Volt VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
32 Byte RX FIFO
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16V2650
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
TXRDYA#
DSRA#
CTSA#
REV. 1.0.2
VCC
RIA#
CDA#
48
45
43
42
41
40
38
47
46
44
39
37
NC
D4
D3
D2
D1
D0
D5
D6
D7
RXB
RXA
1
2
3
4
5
36
35
34
33
RESET
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
A0
A1
A2
NC
TXRDYB# 6
TXA
TXB
7
8
XR16V2650
48-pin TQFP
32
31
30
29
28
27
26
25
OP2B# 9
CSA# 10
CSB# 11
NC 12
15
13
18
19
20
22
16
14
17
21
23
CTSB#
24
NC
RXRDYB#
CDB#
DSRB#
XTAL2
RIB#
GND
D1
31 D4
30 D3
32 D5
29 D2
27
D0
26
28
25
24
23
22
CTSA#
VCC
RTSB#
XTAL1
IOW#
IOR#
D6
D7
RXB
RXA
TXA
TXB
CSA#
CSB#
1
2
3
4
5
6
7
8
XTAL2 11
GND 13
CTSB# 16
IOW# 12
IOR# 14
RTSB# 15
XTAL1 10
9
XR16V2650
32-pin QFN
RESET
RTSA#
INTA
INTB
A0
A1
A2
NC
21
20
19
18
17
ORDERING INFORMATION
P
ART
N
UMBER
XR16V2650IL32
XR16V2650IM
P
ACKAGE
32-Pin QFN
48-Lead TQFP
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
NC
2
XR16V2650
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
N
AME
32-QFN
P
IN
#
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
18
19
20
2
1
32
31
30
29
28
27
14
26
27
28
3
2
1
48
47
46
45
44
19
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
UART channel A Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
UART channel B Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
UART channel A Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel A. See
Table 2
. If it is not
used, leave it unconnected.
UART channel A Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel A. See
Table 2
. If it is not
used, leave it unconnected.
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See
Table 3
. If it is not
used, leave it unconnected.
IOW#
12
15
I
CSA#
CSB#
INTA
7
8
22
10
11
30
I
I
O
INTB
21
29
O
TXRDYA#
-
43
O
RXRDYA#
-
31
O
TXRDYB#
-
6
O
3
XR16V2650
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
Pin Description
N
AME
RXRDYB#
32-QFN
P
IN
#
-
48-TQFP
P
IN
#
18
T
YPE
O
D
ESCRIPTION
UART channel B Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel B. See
Table 2
. If it is not
used, leave it unconnected.
REV. 1.0.2
MODEM OR SERIAL I/O INTERFACE
TXA
5
7
O
UART channel A Transmit Data or infrared encoder data. Standard
transmit and receive interface is enabled when MCR[6] = 0. In this
mode, the TX signal will be HIGH during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared encoder/
decoder interface is LOW. If it is not used, leave it unconnected.
UART channel A Receive Data or infrared receive data. Normal receive
data input must idle HIGH. If this pin is not used, tie it to VCC or pull it
high via a 100k ohm resistor.
UART channel A Request-to-Send (active low) or general purpose out-
put. This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1], and IER[6].
UART channel A Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7], and IER[7]. This
input should be connected to VCC when not used.
UART channel A Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
UART channel A Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel A Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel A Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
Output Port 2 Channel A - The output state is defined by the user and
through the software setting of MCR[3]. INTA is set to the active mode
and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is set to
the three state mode and OP2A# output HIGH when MCR[3] is set to a
logic 0. See MCR[3]. If INTA is used, this output should not be used as
a general output else it will disturb the INTA output functionality.
UART channel B Transmit Data or infrared encoder data. Standard
transmit and receive interface is enabled when MCR[6] = 0. In this
mode, the TX signal will be HIGH during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared encoder/
decoder interface is LOW. If it is not used, leave it unconnected.
UART channel B Receive Data or infrared receive data. Normal receive
data input must idle HIGH. If this pin is not used, tie it to VCC or pull it
high via a 100k ohm resistor.
RXA
4
5
I
RTSA#
23
33
O
CTSA#
25
38
I
DTRA#
DSRA#
-
-
34
39
O
I
CDA#
-
40
I
RIA#
-
41
I
OP2A#
-
32
O
TXB
6
8
O
RXB
3
4
I
4
XR16V2650
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
Pin Description
N
AME
RTSB#
32-QFN
P
IN
#
15
48-TQFP
P
IN
#
22
T
YPE
O
D
ESCRIPTION
UART channel B Request-to-Send (active low) or general purpose out-
put. This port must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1], and IER[6].
UART channel B Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7], and IER[7]. This
input should be connected to VCC when not used.
UART channel B Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel B Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel B Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
Output Port 2 Channel B - The output state is defined by the user and
through the software setting of MCR[3]. INTB is set to the active mode
and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is set to
the three state mode and OP2B# output HIGH when MCR[3] is set to a
logic 0. See MCR[3]. If INTB is used, this output should not be used as
a general output else it will disturb the INTB output functionality.
CTSB#
16
23
I
DTRB#
DSRB#
-
-
35
20
O
I
CDB#
-
16
I
RIB#
-
21
I
OP2B#
-
9
O
ANCILLARY SIGNALS
XTAL1
XTAL2
RESET
10
11
24
13
14
36
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Reset (active high) - A longer than 40 ns HIGH pulse on this pin will
reset the internal registers and all outputs. The UART transmitter output
will be held HIGH, the receiver input will be ignored and outputs are
reset during reset period (see Table 15).
2.25V to 3.6V power supply. All input pins are 5V tolerant.
Power supply common, ground.
The center pad on the backside of the 32-QFN package is metallic and
should be connected to GND on the PCB. The thermal pad size on the
PCB should be the approximate size of this center pad and should be
solder mask defined. The solder mask opening should be at least
0.0025" inwards from the edge of the PCB thermal pad.
No Connection.
VCC
GND
GND
26
13
Center Pad
42
17
N/A
Pwr
Pwr
Pwr
NC
9, 17
12, 24, 25,
37
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
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