TC74HC4049,4050AP/AF/AFT
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74HC4049AP, TC74HC4049AF, TC74HC4049AFT
TC74HC4050AP, TC74HC4050AF, TC74HC4050AFT
TC74HC4049AP/AF/AFT
TC74HC4050AP/AF/AFT
Hex
Buffer/Converter
(inverting)
Hex
Buffer/Converter
TC74HC4049AP, TC74HC4050AP
The TC74HC4049A and TC74HC4050A are high speed CMOS
HEX BUFFERs fabricated with silicon gate C
2
MOS technology.
They achieve the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
The TC74HC4049A is an inverting buffer, while the
TC74HC4050A is a non-inverting buffer. The internal circuits are
composed of 3-stages (HC4049A) or 2-stages (HC4050A) of
invertaers, which provided high noise immunity and stable
output.
Input protection circuits are different from those of other high
speed CMOS IC’s. They eliminate the diodes on the V
CC
side
thus providing of logic-level conversion from high-level volages
up to 15 V to low-level voltages.
They are useful for battery back up circuits, because input
voltage can be applied on IC’s which are not biased by V
CC
.
TC74HC4049AF, TC74HC4050AF
TC74HC4049AFT, TC74HC4050AFT
Features
•
•
•
•
•
•
•
•
High speed: t
pd
=
9 ns (typ.) at V
CC
=
5 V
Low power dissipation: I
CC
=
1
μA
(max) at Ta
=
25°C
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
Output Drive Capability: 15 LSTTL loads
Symmetrical output impedance: |I
OH
|
=
I
OL
=
6 mA (min)
Balanced propagation delays: t
pLH
∼
t
pHL
−
Wide operating voltage range: V
CC (opr)
=
2 V to 6 V
Pin and function compatible with 4049B/4050B
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
TSSOP16-P-0044-0.65A
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.06 g (typ.)
Start of commercial production
1986-05
1
2014-03-01
TC74HC4049,4050AP/AF/AFT
Absolute Maximum Ratings (Note 1)
Characteristics
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
Rating
−
0.5 to 7
−
0.5 to 18
−
0.5 to V
CC
+
0.5
−
20
±
20
±
35
±
75
Unit
V
(Note 2)
V
V
mA
mA
mA
mA
mW
°C
500 (DIP) (Note 3)/180 (SOP/TSSOP)
−
65 to 150
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: DC input voltage (V
IN
) specified is measured to GND and is not related to V
CC
.
Recommended operating range is 0 V to 15 V and it is possible to convert logic-levels from 15 V to 5 V or 5
V to 2 V.
Note 3: 500 mW in the range of Ta
= −40
to 65°C. From Ta
=
65 to 85°C a derating factor of
−10
mW/°C shall be
applied until 300 mW.
Operating Ranges (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Operating temperature
Symbol
V
CC
V
IN
V
OUT
T
opr
Rating
2 to 6
0 to 15
0 to V
CC
−
40 to 85
Unit
V
V
V
°C
0 to 1000 (V
CC
=
2.0 V)
Input rise and fall time
t
r
, t
f
0 to 500 (V
CC
=
4.5 V)
0 to 400 (V
CC
=
6.0 V)
ns
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either V
CC
or GND.
3
2014-03-01
京公网安备 11010802033920号
EEWORLD
