EEWORLDEEWORLDEEWORLD

Part Number

Search

8P34S1212NLGI

Description
IC CLK BUFFER 2:12 1.2GHZ 40VQFN
Categorysemiconductor    Analog mixed-signal IC   
File Size536KB,19 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance
Download Datasheet Parametric View All

8P34S1212NLGI Online Shopping

Suppliers Part Number Price MOQ In stock  
8P34S1212NLGI - - View Buy Now

8P34S1212NLGI Overview

IC CLK BUFFER 2:12 1.2GHZ 40VQFN

8P34S1212NLGI Parametric

Parameter NameAttribute value
typefanout buffer (allocation), multiplexer
Number of circuits1
Ratio - Input:Output2:12
Differential - Input:OutputYes Yes
enterCML,LVDS
outputLVDS
Frequency - maximum1.2GHz
Voltage - Power1.71 V ~ 1.89 V
Operating temperature-40°C ~ 85°C
Installation typesurface mount
Package/casing40-VFQFN Exposed Pad
Supplier device packaging40-VFQFPN(6x6)
1:12 LVDS Output 1.8V Fanout Buffer
IDT8P34S1212I
Datasheet
Description
The IDT8P34S1212I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8P34S1212I is characterized to operate from a 1.8V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8P34S1212I ideal for those clock
distribution applications that demand well-defined performance and
repeatability.
Two selectable differential inputs and 12 low skew outputs are
available. The integrated bias voltage reference enables easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.
Features
12 low skew, low additive jitter LVDS output pairs
Two selectable, differential clock input pairs
Differential CLK0, CLK1 pairs can accept the following differential
input levels: LVDS, CML
Maximum input clock frequency: 1.2GHz (maximum)
LVCMOS/LVTTL interface levels for the control input select pin
Output skew: 10ps (typical)
Propagation delay: 340ps (typical)
Low additive phase jitter, RMS; f
REF
= 156.25MHz, V
PP
= 1V,
12kHz- 20MHz: 41fs (typical)
Maximum device current consumption (I
DD
): 227mA (maximum)
at 1.89V
Full 1.8V supply voltage
Lead-free (RoHS 6), 40-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
Q0
nQ0
Q1
nQ1
Q2
nQ2
V
DD
Pin Assignment
GND
30
29
28
27
26
25
24
23
22
V
DD
31
Q8
32
nQ8
33
Q9
34
nQ9
35
Q10
36
nQ10
37
Q11
38
nQ11
39
V
DD
40
1
2
3
4
5
6
7
8
9
10
GND
21
20
V
DD
19
nQ3
18
Q3
17
nQ2
16
Q2
15
nQ1
14
Q1
13
nQ0
12
Q0
11
V
DD
nQ7
nQ6
nQ5
nQ4
Q7
Q6
Q5
IDT8P34S1212I
40-Lead VFQFN
6.0mm x 6.0mm x 0.90mm
package body
4.65mm x 4.65mm ePad Size
NL Package
Top View
CLK0
nCLK0
f
REF
V
DD
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
VREF
CLK1
nCLK1
SEL
Q9
nQ9
Q10
nQ10
V
REF
V
REF
Q11
nQ11
©2017 Integrated Device Technology, Inc.
1
nCLK0
CLK0
CLK1
nCLK1
V
DD
V
DD
nc
Q4
SEL
November 24, 2017
nc
Analog integrated circuit EDA technology and design: simulation and layout examples
This book is one of the planned textbooks in the series of microelectronics and integrated circuit design. The whole book follows the full-custom design process of analog integrated circuits and intro...
arui1999 Download Centre
Recruiting sales representatives (Shanghai area)--Famous Korean encryption chip company
[font=Helvetica][size=14px]In order to expand its business in Shanghai, a famous Korean encryption chip company is now recruiting a sales representative (Shanghai area). [/size][/font] [font=Helvetica...
happyangliu Recruitment
Hello everyone, who can introduce the interface circuit between user interface circuit chip PBL38710 and CPLD?
The connection of PBL38710/1 in the user circuit is shown in Figure 3. The user's telephone is connected to OVP through the TIP and RING lines, and then connected to the TIPX and RINGX pins of PBL3871...
bhyangyong FPGA/CPLD
High-voltage, high-brightness LED driver
By Dave Priscak, Systems Applications Manager, Texas Instruments (TI) As countries move away from incandescent light bulbs and companies realize the energy savings that can be achieved by switching to...
德州仪器 Analogue and Mixed Signal
The process of WEBENCH design + a K-type thermocouple sensor circuit design
1. Design topic: Design of a K-type thermocouple sensor circuit Use webench software tool to design a K-type thermocouple sensor circuit 2. Design process Select thermocouple sensor on webench pageSta...
qwqwqw2088 Analogue and Mixed Signal
How to get weather forecast data with ESP8266
Once upon a time, I had been thinking about how to realize some temperature, humidity, longitude and latitude data without sensors, until I thought of obtaining them from the weather forecast base sta...
wateras1 RF/Wirelessly

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2457  2911  717  2299  693  50  59  15  47  14 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号