R
EM MICROELECTRONIC -
MARIN SA
V6118
2, 4 and 8 Mutiplex LCD Driver
Description
The V6118 is a universal low multiplex LCD driver. The
version V6118 2 drives two ways multiplex (two
blackplanes) LCD, the version V6118 4, four way
multiplex LCD , and the V6118 8, eight way multiplex
LCD. The display refresh is handled on chip via a 40 x 8
bit RAM which holds the LCD content driven by the driver.
LCD pixels (or segments) are addressed on a one to one
basis with the 40 x 8 bit RAM (a set bit corresponds to an
activated LCD pixel). The V6118 has very low dynamic
current consumption , 150 µA max., making it particularly
attractive for portable and battery powered applications.
The wide operating range on both the logic (V
DD
) and the
LCD (V
LCD
) supply voltages offers much application
flexibility. The LCD bias generation is internal. The voltage
bias levels can also be provided externally for applications
having large pixels sizes. The V6118 can be used as a
column only driver for cascading in large display
applications. In the column only mode, 40 column outputs
are available to address the display. A BLANK function is
provided to blank the LCD, useful at power up to hold the
display blank until the microprocessor has updated the
display RAM.
Features
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V6118 2 is 2 way multiplex with 2 rows and 38 columns
V6118 4 is 4 way multiplex with 4 rows and 36 columns
V6118 8 is 8 way multiplex with 8 rows and 32 columns
Low dynamic current, 150 µA max.
Low standby current, 1 µA max. at +25°C
Voltage bias and mux signal generation on chip
Display refresh on chip, 40 x 8 RAM for display storage
Display RAM addressable as 8, 40 bits words
Column driver only mode to have 40 column outputs
Crossfree cascadable for large LCD applications
Separate logic and LCD supply voltage pins
Wide power supply range: V
DD
: 2 to 6V, V
LCD
: 2 to 8V
BLANK function for LCD blanking on power up etc.
Voltage bias inputs for applications with large pixel
sizes
Bit mapped
Serial input / output
Very low external component count
-40 to + 85 °C temperature range
No busy states
LCD updating synchronized to the LCD refresh signal
QFP52 and TAB packages
Applications
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Balances and scales
Automotive displays
Utility meters
Large displays (public information panel etc.)
Pagers
Portable, battery operated products
Telephones
Typical Operating Configuration
Pad Assignment
Fig. 1
Fig. 2
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©
2004, EM Microelectronic-Marin SA
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V6118
Absolute Maximum Ratings
Parameter
Symbol
Conditions
Supply voltage range
V
DD
-0.3V to + 8V
LCD supply voltage range
V
LCD
-0.3V to + 9V
Voltage at DI, DO, CLK,
V
LOGIC
-0.3V to V
DD
+0.3V
STR, FR,
COL
Voltage at V1 to V3, S1 to
V
DISP
-0.3V to V
LCD
+ 0.3V
S40
Storage temperature range
T
STO
-65 to +150°C
Power dissipation
P
MAX
100mW
Electrostatic
discharge
max. to MIL-STD-883C
V
SMAX
1000V
method 3015.7 with ref. to
V
SS
Maximum soldering
T
S
250°C x 10s
conditions
Table 1
Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, anti-static
precautions must be taken as for any other CMOS
component. Unless otherwise specified, proper operation
can only occur when all terminal voltages are kept within
the voltage range. Unused inputs must always be tied to
a defined logic voltage level.
Operating Conditions
Parameter
Symbol Min
Operating
T
A
-40
Temperature
Logic supply voltage
V
DD
2
LCD supply voltage
V
LCD
2
Typ
5
5
Max Unit
+85 °C
6
8
V
V
Table 2
Stresses above these listed maximum ratings may cause
permanent damages to the device. Exposure beyond
specified operating conditions may affect device
reliability or cause malfunction.
Electrical Characteristics
V
DD
= 5V ±10%, V
LCD
= 2 to 7V and T
A
= -40 to +85°C, unless otherwise specified
Parameter
Symbol
Test Conditions
Min.
Dynamic supply current
I
LCD
See note 1
Dynamic supply current
I
DD
See note 1 at T
A
= 25°C
Dynamic supply current
I
DD
See note 1
Dynamic supply current
I
DD
See note 2
Standby supply current
I
SS
See note 3 at T
A
= 25°C
Control Signals DI, CLK, STR, FR
and
COL
Input leakage
I
IN
0 < V
IN
< V
DD
Input capacitance
C
IN
at T
A
= 25°C
Low level input voltage
V
IL
0
High level input voltage for DI, STR, V
IH
2.0
FR and
COL
High level input voltage for CLK
V
IH
3.0
Data Output DO
High level output voltage
V
OH
I
H
= 4 mA
2.4
Low level output voltage
V
OL
I
L
= 4 mA
Driver Outputs S1 … S40
Driver impedance (note 4)
R
OUT
I
OUT
= 10µA, V
LCD
= 7V
Driver impedance (note 4)
R
OUT
I
OUT
= 10µA, V
LCD
= 3V
Driver impedance (note 4)
R
OUT
I
OUT
= 10µA, V
LCD
= 2V
Bias impedance V1, V2, V3 (note 5) R
BIAS
I
OUT
= 10µA, V
LCD
= 7V
Bias impedance V1, V2, V3 (note 5) R
BIAS
I
OUT
= 10µA, V
LCD
= 3V
Bias impedance V1, V2, V3 (note 5) R
BIAS
I
OUT
= 10µA, V
LCD
= 2V
DC output component
± V
DC
see Tables 4a & 4b,
V
LCD
= 5V
Note 1:
Note 2:
Note 3:
Note 4:
Typ.
100
0.1
3
200
0.1
Max.
150
1
12
250
1
Units
µA
µA
µA
µA
µA
1
8
100
0.8
V
DD
V
DD
nA
pF
V
V
V
V
V
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
mV
Table 3
0.4
0.5
1.2
9
16
18
30
30
1.5
2.5
20
25
50
All outputs open, STR at V
SS
, FR = 400 Hz, all other inputs at V
DD
.
All outputs open, STR at V
SS
, FR = 400 Hz, f
CLK
= 1 MHz, all other inputs at V
DD
.
All outputs open, all other inputs at V
DD
.
This is the impedance between of the voltage bias level pins (V1, V2 or V3) and the output pins S1 to S40
when a given voltage bias level is driving the outputs (S1 to S40)
Note 5:
This is the impedance seen at the segment pin. Outputs measured one at a time.
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V6118
Column Drivers
Outputs
FR Polarity
S1 to S40
logic 1
S1 to S40
logic 0
S1 to S40
S1 to S40
logic 1
logic 0
COL
logic 0
logic 0
Column Data
logic 1
logic 1
logic 0
logic 0
Measured*
⏐
Sx* - V
SS
⏐
⏐
V
LCD
- Sx*
⏐
⏐
⏐
V
LCD
- Sx*
⏐
Sx* - V
SS
⏐
Guaranteed
logic 0
logic 0
¦ V
LCD
- Sx* ¦ = ¦ Sx* - V
SS
¦ ± 25 mV
¦ V
LCD
- Sx* ¦ = ¦ Sx* - V
SS
¦ ± 25 mV
Table 4a
*Sx = the output number (ie. S1 to S40)
Row Drivers
Outputs
S1 to Sn*
S1 to Sn*
S1 to Sn*
S1 to Sn*
FR Polarity
logic 1
logic 0
logic 1
logic 0
COL
logic 1
logic 1
Column Data
logic 1
logic 1
logic 0
logic 0
Measured*
⏐
V
LCD
- Sx
⏐
⏐
Sx - V
SS
⏐
⏐
⏐
Sx - V
SS
⏐
V
LCD
- Sx
⏐
Guaranteed
logic 1
logic 1
¦ V
LCD
- Sx ¦ = ¦ Sx - V
SS
¦ ± 25 mV
¦ V
LCD
- Sx ¦ = ¦ Sx - V
SS
¦ ± 25 mV
Table 4b
*n = the V6118 version no. (ie. 2, 4 or 8)
Timing Characteristics
V
DD
= 5V ± 10%, V
LCD
= 2 to 8V and T
A
= -40 to +85°C
Parameter
Symbol
Test Conditions
Clock high pulse width
t
CH
Clock low pulse width
t
CL
Clock and FR rise time
t
CR
Clock and FR fall time
t
CF
Data input setup time
t
DS
Data input hold time
t
DH
Data output propagation
t
PD
C
LOAD
= 50pF
STR pulse width
t
STR
CLK falling to STR rising
t
P
STR falling to CLK falling
t
D
FR frequency (vers. 2/4/8)
F
FR
(note 2)
Min.
120
120
Typ.
Max.
200
200
20 (note 1)
30 (note 1)
100
100
10
200
128/256/512
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
Table 5a
Note 1:
t
DS
+ t
DH
minimum must be
≥
100 ns. If t
DS
= 20 ns then t
DH
≥
80ns.
Note 2:
V6118 n, FR = n times the desired LCD refresh rate where n is the V6118 version number.
V
DD
= 2 to 6V, V
LCD
= 2 to 8V and T
A
= -40 to +85°C
Parameter
Symbol
Test Conditions
Clock high pulse width
t
CH
Clock low pulse width
t
CL
Clock and FR rise time
t
CR
Clock and RF fall time
t
CF
Data input setup time
t
DS
Data input hold time
t
DH
Data output propagation
t
PD
C
LOAD
= 50pF
STR pulse width
t
STR
CLK falling to STR rising
t
P
STR falling to CLK falling
t
D
FR frequency (Vers. 2/4/8)
F
FR
(note 2)
Min.
500
500
Typ.
Max.
200
200
100 (note 1)
150 (note 1)
400
500
10
1
128/256/512
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Hz
Table 5b
Note 1:
t
DS
+ t
DH
minimum must be
≥
500 ns. If t
DS
= 100 ns then t
DH
≥
400ns.
Note 2:
V6118 n, FR = n times the desired LCD refresh rate where n is the V6118 version number.
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V6118
Timing Waveforms
Fig. 3
V6118 Data Transfer Cycle,
COL
Inactive
V6118 as a row and column driver (
COL
inactive)
40 bit load cycle, RAM address provided by
address command bits 1 to (n*).
Address Bits
Addr. 1 to Addr. n*
V6118 2
V6118 4
V6118 8
Display RAM
Address
LCD Row
(Note1)
10
1000
10000000
10000000
Row 1
01
0100
01000000
01000000
Row 2
0010
00100000
00100000
Row 3
0001
00010000
00010000
Row 4
00001000
00001000
Row 5
00000100
00000100
Row 6
00000010
00000010
Row 7
00000001
00000001
Row 8
Note1: A set address bit corresponds to a write enabled RAM
address, the same data can be written to more than one RAM
address by setting the required address bits .
Fig. 4
V6118 Data Transfer Cycle,
COL
Active
V6118 as a column driver (
COL
active)
48 bit load cycle, RAM address provided by
address command bits 1 to 8.
Address Bits
Addr. 1 to Addr. 8
V6118 2
V6118 4
V6118 8
Display RAM
Address
LCD Row
(Note1)
10000000
100000000
10000000
10000000
Row 1
01000000
01000000
01000000
01000000
Row 2
00100000
00100000
00100000
Row 3
00010000
00010000
00010000
Row 4
00001000
00001000
Row 5
00000100
00000100
Row 6
00000010
00000010
Row 7
00000001
00000001
Row 8
Note1: A set address bit corresponds to a write enabled RAM
address, the same data can be written to more than one RAM
address by setting the required address bits .
Fig. 5
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V6118
Block Diagram
Note 1:
When logic “1” the STR input forces the display RAM address 10000000 (which corresponds to row 1)
has to be selected by the 8 bit sequences. Cascaded V6118s are synchronized in this way. The LCD
picture is rebuilt starting from row 1 each time data is written to the display RAM.
Fig. 6
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