AN090
Getting Started
1. Introduction
This application note will help developers quickly implement proof-of-concept designs using the
KX222,
and
KX224
tri-axis accelerometers. Please refer to the corresponding Product Specifications
document for additional implementation guidelines. Kionix strives to ensure that our accelerometers
will meet design expectations by default, but it is not possible to provide default setting to work in
every environment. Depending on the intended application, it is very likely that some customization
will be required to optimize performance. The information provided here will help the developer get
the most out of these tri-axis accelerometers.
2. Circuit Schematic
This section shows recommended wiring for this family of accelerometers, based on proven
operation of the part. Specific applications may require modifications from these recommendations.
Please refer to the corresponding Product Specifications document for all pin descriptions.
Figure 1:
KX222 Application Schematic
36 Thornwood Dr.
—
Ithaca, NY 14850 USA
Tel: 607-257-1080
—
Fax: 607-257-1146
www.kionix.com
—
info@kionix.com
© Kionix 2017 All Rights Reserved
21 December 2017
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AN090
Figure 2:
KX224 Application Schematic
3. Quick Start Implementations
Here we present several basic ways to initialize the part. These can vary based on desired operation,
but generally the initial operations a developer wants to do are: 1) read back acceleration data
asynchronously, 2) read back acceleration data when next data is ready via interrupt (synchronous
data reading), 3) use of the sample buffer, 4) use the Wake-Up function, 5) activate the tilt position
function, 6) activate the tap/double-tap function, and 7) activate the free-fall function. These cursory
solutions are provided as a means for configuring the part to a known operational state. Note that
these conditions just provide a starting point, and the values may vary as developers refine their
application requirements.
4. Asynchronous Read Back Acceleration Data (Setting G-Range and ODR)
-
Write 0x40 to Control Register 1 (CNTL1) to set the accelerometer in stand-by mode, to set
the performance mode to High Resolution (full power) and G-range to ±8g.
Register Name
CNTL1
-
Address
0x18
Value
0x40
Write 0x02 to Data Control Register (ODCNTL) to set the Output Data Rate (ODR) of the
accelerometer to 50 Hz. (Note: This is also the default value.)
Register Name
ODCNTL
Address
0x1B
Value
0x02
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AN090
-
Write 0xC0 to Control Register 1 (CNTL1) to set the accelerometer into operating mode (PC1
= 1)
Register Name
CNTL1
-
Address
0x18
Value
0xC0
Acceleration data can now be read from the XOUT_L, XOUT_H, YOUT_L, YOUT_H,
ZOUT_L, and ZOUT_H registers in 2’s complement format.
5. Synchronous Hardware Interrupt Read Back Acceleration Data (Setting G-
Range and ODR)
-
Write 0x60 to Control Register 1 (CNTL1) to set the accelerometer in stand-by mode, to set
the performance mode to High Resolution (full power), G-range to ±8g and enable the
availability of new data as an interrupt.
Register Name
CNTL1
-
Address
0x18
Value
0x60
Write 0x38 to Interrupt Control Register (INC1) to enable physical interrupt pin INT1, to set
the polarity of the physical interrupt to active high and to transmit interrupt pulse with a period
of 0.03 to 0.05 msec.
Register Name
INC1
Address
0x1C
Value
0x38
-
Write 0x10 to Interrupt Control Register 4 (INC4) to set the Data Ready interrupt to be
reported on physical interrupt pin INT1.
Register Name
INC4
Address
0x1F
Value
0x10
-
Write 0x02 to Output Data Rate (ODR) Control Register (ODCNTL) to set the ODR of the
accelerometer to 50 Hz. (Note: This is also the default value.)
Register Name
ODCNTL
Address
0x1B
Value
0x02
-
Write 0xE0 to Control Register 1 (CNTL1) to set the accelerometer into operating mode (PC1
= 1)
Register Name
CNTL1
Address
0x18
Value
0xE0
-
Acceleration data can now be read from the XOUT_L, XOUT_H, YOUT_L, YOUT_H,
ZOUT_L, and ZOUT_H registers in 2’s complement format. Also, the interrupt would be
reflected in Bit4 (INT) of STATUS_REG and Bit4 (DRDY) in INS2 register.
© Kionix 2017 All Rights Reserved
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AN090
6. Sample Buffer Operation
6.1.
Sample Buffer-Full Interrupt via Physical Hardware Interrupt
-
Write 0x00 to Control Register 1 (CNTL1) to set the accelerometer in stand-by mode, to
set the performance mode of the accelerometer to Low Power mode, and G-range to ±8g.
Register Name
CNTL1
-
Address
0x18
Value
0x00
Write 0x38 to Interrupt Control Register (INC1) to enable physical interrupt pin INT1, to set
the polarity of the physical interrupt to active high and to transmit interrupt pulse with a
period of 0.03 to 0.05 msec.
Register Name
INC1
Address
0x1C
Value
0x38
-
Write 0x40 to Interrupt Control Register 4 (INC4) to set the Buffer Full interrupt to be
reported on physical interrupt pin INT1.
Register Name
INC4
Address
0x1F
Value
0x40
-
Write 0x02 to Output Data Rate (ODR) Control Register (ODCNTL) to set the ODR of the
accelerometer to 50 Hz. (Note: This is also the default value.)
Register Name
ODCNTL
Address
0x1B
Value
0x02
-
Write 0xA0 to Buffer Control Register 2 (BUF_CNTL2) to activate the sample buffer, to set
the resolution of the acceleration data samples collected to 8 bits, to enable report of the
interrupt status in INS2, and set the operating mode of the sample buffer to FIFO.
Register Name
BUF_CNTL2
Address
0x3B
Value
0xA0
-
Write 0x80 to Control Register 1 (CNTL1) to set the accelerometer into operating mode
(PC1 = 1)
Register Name
CNTL1
Address
0x18
Value
0x80
-
Once Buffer-Full Interrupt is issued on INT1 pin, acceleration data can then be read from
the Buffer Read (BUF_READ) register at address 0x3F in 2’s complement format. Also,
the interrupt would be reflected in Bit4 (INT) of STATUS_REG register and Bit6 (BFI) of
INS2 register. Since the resolution of the samples data was set to 8-bit, only the most
significant 8 bits of each sample will be stored in the buffer, and recorded in the following
order: X_HIGH, Y_HIGH, Z_HIGH with the oldest data point read first as it is a FIFO
buffer. The full buffer contains 2043 X, Y, Z elements, which corresponds to 681 unique
acceleration data samples.
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AN090
6.2.
-
Trigger Mode Buffer Operation
Ensure that the TRIG pin is can be controlled via hardware or software. The pin should be
held low (inactive state) and be driven high to activate the internal trigger event.
Write 0x00 to Control Register 1 (CNTL1) to set the accelerometer in stand-by mode, to
set the performance mode of the accelerometer to Low Power mode, and G-range to ±8g.
Register Name
CNTL1
-
Address
0x18
Value
0x00
-
Write 0x38 to Interrupt Control Register (INC1) to enable physical interrupt pin INT1, to set
the polarity of the physical interrupt to active high and to transmit interrupt pulse with a
period of 0.03 to 0.05 msec.
Register Name
INC1
Address
0x1C
Value
0x38
-
Write 0x40 to Interrupt Control Register 4 (INC4) to set the Buffer Full interrupt to be
reported on physical interrupt pin INT1.
Register Name
INC4
Address
0x1F
Value
0x40
-
Write 0x02 to Data Control Register (ODCNTL) to set the Output Data Rate (ODR) of the
accelerometer to 50 Hz. (Note: This is also the default value).
Register Name
ODCNTL
Address
0x1B
Value
0x02
-
Choose desired number of samples to collect before and after a trigger event. To begin,
we need to know the capacity of the buffer. The buffer has the capability of storing 2048
bytes of data. Design constraints limit the number of samples in the buffer to
rounddown(2048/dataset_in_bytes)-1.
Consider 16-bit data being stored into the buffer
and a complete
dataset_in_bytes=6
(3
axes * 2 bytes/axis).
The resulting number of
samples that can be stored in the buffer is
rounddown(2048/6)-1=340.
For this example,
we will save time by only collecting a single sample after a trigger event. This means we
need to set a threshold of 339 samples (340-339=1 sample of data after a trigger event).
The sample threshold is stored in register space across 2 different registers BUF_CNTL1
(lower 8 bits) and BUF_CNTL2 (bits 9 and 10). The following is an illustration of what
values need to be written to the buffer threshold low and high bytes:
int
smp_th = 339;
char
smp_th_l = (smp_th & 0xFF);
char
smp_th_h = ((smp_th >> 8) & 0xFF);
// 0x53
// 0x01
-
Write 0x53 to Buffer Control Register 1 (BUF_CNTL1) as this is the value for
BUF_TH[7:0].
Register Name
BUF_CNTL1
Address
0x3A
Value
0x53
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21 December 2017
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