DEMO MANUAL DC1805A
LTC6362
Driving 18-Bit SAR ADC
Description
The LTC
®
6362 is a low power, low noise differential op
amp with rail-to-rail input and output swing that has been
optimized to drive low power SAR ADCs. The amplifier
may be configured to buffer a fully differential input signal
or convert a single-ended input signal to a differential
output signal.
The LTC2380/LTC2379/LTC2378/LTC2377/LTC2376 are low
power, low noise ADCs with serial outputs that can operate
from a single 2.5V supply. The DC1805A demonstrates
the DC and AC performance of the LTC6362 driving the
LTC2379-18 when used in conjunction with the DC590B
QuikEval™ and DC718 fast DACs data collection boards.
Use the DC590B to demonstrate DC performance such
as peak-to-peak noise and DC linearity. Use the DC718
if precise sampling rates are required or to demonstrate
AC performance such as SNR, THD, SINAD and SFDR.
The DC1805A is intended to demonstrate recommended
grounding, component placement and selection, routing
and bypassing for LTC6362 and the ADC.
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
QuikEval and PScope are trademarks of Linear Technology Corporation. All other trademarks are
the property of their respective owners.
Figure 1. DC1805A Connection Diagram
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DEMO MANUAL DC1805A
Description
Table 1. DC1805A Assembly Options
ASSEMBLY VERSION
DC1805A-A
DC1805A-B
DC1805A-C
DC1805A-D
DC1805A-E
DC1805A-F
DC1805A-G
DC1805A-H
PART NUMBER
LTC2380CMS-16
LTC2378CMS-16
LTC2377CMS-16
LTC2376CMS-16
LTC2379CMS-18
LTC2378CMS-18
LTC2377CMS-18
LTC2376CMS-18
MAX CONVERSION RATE
2Msps
1Msps
500ksps
250ksps
1.6Msps
1Msps
500ksps
250ksps
NUMBER OF BITS
16
16
16
16
18
18
18
18
MAX CLK IN FREQUENCY
100MHz
50MHz
25MHz
12.5MHz
99.2MHz
62MHz
31MHz
15.5MHz
Quick start proceDure
Figure 2. DC1805A Test Diagram
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DEMO MANUAL DC1805A
Quick start proceDure
This board is tested by measuring the distortion at the
differential output given a –1dBFS, 2kHz single-ended
input as shown in Figure 2.
For SINAD, THD or SNR testing a low noise, low distor-
tion generator such as Audio Precision SYS-2722, B&K
Type 1051 or Stanford Research DS360 should be used.
A low jitter RF oscillator such as the Marconi Instruments,
Multisource Generator 2026 should be used as the clock
source.
To test the boards please follow the steps below:
1) Make sure that all the jumpers are set as shown in
Figure 2 (DC1805A Test Diagram).
2) Power up the board by applying 9VDC.
3) Apply the clock signal to connector J1. Clock frequency
99.2MHz (to achieve 1.6Msps conversion rate, please
refer to the Clock Source section for more detailed
information), V
IN
3.3V
P-P
.
4) A single pole lowpass filter should be used for best
SNR measurement data. One option is to create an on-
board RC low pass filter by populating R5 with 200Ω
and C33 with 0.22µF It is very important to use a very
.
low distortion capacitor. In order to balance both inputs
of the LTC6362 populate R12 with a 200Ω resistor in
parallel with a 0.22µF capacitor.
5) Apply a 2kHz, –1dBFS signal to connector J3.
The performance that results from these connections are
displayed in Figure 4.
Dc718 Quick start proceDure
Check to make sure that all switches and jumpers are
set as shown in the connection diagram of Figure 1. The
default connections configure the ADC to use the onboard
reference and regulators to generate the required common
mode voltages. The analog input is DC coupled. Connect
the DC1805A to a DC718 USB high speed data collection
board using connector J4. Then, connect the DC718 to a
host PC with a standard USB A/B cable. Apply 9V to the
indicated terminals. Then apply a low jitter signal source
to J3. Connect a low jitter 100MHz 3.3V
P-P
sine wave or
square wave to connector J1. Note that J1 has a 50Ω
termination resistor to ground.
Run the QuikEval-II software (Pscope.exe version K72
or later) supplied with the DC718 or download it from
www.linear.com.
Complete software documentation is available from the
Help menu. Updates can be downloaded from the Tools
menu. Check for updates periodically as new features
may be added.
The PScope™ software should recognize the DC1805A
and configure itself automatically.
Click the Collect button (see Figure 4) to begin acquiring
data. The Collect button then changes to Pause, which
can be clicked to stop data acquisition.
Dc590B setup
IMPORTANT! To avoid damage to the DC1805A, make
sure that VCCIO (JP5) is set to 3.3V before connecting
the DC590B to the DC1805A.
Connect the DC590B to a host PC with a standard USB
A/B cable. Connect the DC1805A to a DC590B USB serial
controller using the supplied 14-conductor ribbon cable.
Run the evaluation software supplied with the DC590B or
download it from
www.linear.com.
The correct control panel will be loaded automatically. Click
the Collect button to begin reading the ADC.
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DEMO MANUAL DC1805A
Dc1805a setup
DC Power
The DC1805A requires 9VDC and draws less than 70mA.
Most of the supply current is consumed by the CPLD,
regulators and discrete logic on the board. The 9VDC input
voltage powers the LTC6362 and the ADC through LT
®
1763
regulators which provide protection against accidental
reverse bias. Additional regulators provide power for the
CPLD. See Figure 1 for connection details.
Clock Source
You must provide a low jitter 3.3V
P-P
maximum sine or
square wave to J1. The clock input is AC-coupled so the
DC level of the clock signal is not important. A genera-
tor like the Marconi Instruments, Multisource Generator
2026, HP8644 or the DC1216A-A is recommended. Even
a good generator can start to produce noticeable jitter at
low frequencies. Therefore it is recommended for lower
sample rates to divide down a higher frequency clock
to the desired sample rate. The ratio of clock frequency
to conversion rate is 62:1 for 18-bit parts and 50:1 for
16-bit parts. If the clock input is to be driven with logic,
it is recommended that the 50Ω terminator (R1) be re-
moved. Slow rising edges may compromise the SNR of
the converter in the presence of high amplitude higher
frequency input signals.
Reference
The default reference is a LTC6655 5V reference. An external
reference can be used by removing (U3) and populating
(R6) with 0 resistor. If an external reference is used it must
settle quickly in the presence of glitches on the REF pin.
Analog Input
LTC6362 drives the analog input of the LTC2379-18 on
the DC1805A as shown in Figure 3. This circuit converts
a single-ended input signal to a differential output signal
applied at the ADC inputs. Please refer to the LTC6362 data
sheet for various configurations of the LTC6362 interface
to the SAR ADC.
AC-coupling the input may degrade the distortion per-
formance of the ADC due to nonlinearity of the coupling
capacitor.
Component Selection
When driving a low noise, low distortion ADC such as
the LTC2379-18 with the LTC6362, component selection
is important so as to not degrade performance. Resistors
should have low values to minimize noise and distortion.
Metal film resistors are recommended to reduce distortion
caused by self heating. To further reduce distortion, NPO
or silver mica capacitors should be used because of their
low voltage coefficients.
R17
1k
R15
1k
R26
1k
R18
35.7Ω
C27
NPO
3900pF
R19
0Ω
0402
+
LTC6362
A
IN
+
–
R28
35.7Ω
C26
NPO
3900pF
+
R19
0Ω
0402
C29
NPO
3900pF
LTC2379-18
–
DC1805A F03
R27
1k
Figure 3. LTC6362 Ground Referenced Single-Ended to Differential Converter
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DEMO MANUAL DC1805A
Dc1805a setup
Jumpers
JP1
– Sets the DC bias for V
OCM
of the LTC6362 to be
internally biased or externally driven. The voltage on this
pin sets the output common mode voltage level. V
REF
/2
is the default setting.
JP2
– Toggles the LTC6362 On and Off. Part On (5V) is
the default setting.
JP3
– In the REF position the Digital Gain Compression
is off and the analog input range at ADC inputs is 0V to
V
REF
. In the GND position Digital Gain Compression is
turned on and the analog input range at ADC inputs is
0.1V
REF
to 0.9V
REF
.
JP4
– Ties the WP pin to V
CC
or GND. WP is the hardware
write-protect pin. If tied to V
CC
, hardware write protection
is enabled. If WP is tied to GND, the hardware write-
protection is disabled.
JP5
– VCCIO sets the output levels at J3 to either 3.3V
or 2.5V. Use 3.3V to interface to the DC718 which is the
default setting.
Figure 4. PScope Screenshot
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