UPSD3334D-40T6 datasheet, PDF - EEWORLD Datasheet

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UPSD3334D-40T6: Description8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP52; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，272 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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UPSD3334D-40T6 Overview

8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP52

UPSD3334D-40T6 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	QFP
Contacts	52
Reach Compliance Code	compli
bit size	8
CPU series	8051
JESD-30 code	S-PQFP-G52
JESD-609 code	e3
Humidity sensitivity level	1
Number of terminals	52
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP52,.47SQ
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	8192
rom(word)	262144
ROM programmability	FLASH
speed	40 MHz
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

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UPSD33xx

Turbo series

fast 8032 MCU with programmable logic

Features

■

Fast 8-bit Turbo 8032 MCU, 40 MHz

– Advanced core, 4-clocks per instruction

– 10 MIPs, peak performance at 40 MHz

(5 V)

– JTAG debug and in-system programming

– Branch cache and6 instruction prefetch

queue

– Dual XDATA pointers with auto increment

and decrement

– Compatible with 3rd party 8051 tools

Dual Flash memories with memory

management

– Place either memory into 8032 program

address space or data address space

– Read-while-write operation for in-

application programming and EEPROM

emulation

– Single voltage program and erase

– 100K guaranteed erase cycles, 15-year

retention

Clock, reset, and supply management

– Flexible 8-level CPU clock divider register

– Normal, Idle, and Power-down modes

– Power-on and low voltage reset supervisor

– Programmable watchdog timer

Programmable logic, general purpose

– 16 macrocells

– Create shifters, state machines, chip-

selects, glue-logic to keypads, panels,

LCDs, others

■

LQFP52 (T) 52-lead, thin, quad, Flat

LQFP80 (U) 80-lead, thin, quad, flat

■

Packages are ECOPACK

Communication interfaces

– I

C master/slave controller, 833 kHz

– SPI master controller, 10 MHz

– Two UARTs with independent baud rate

– IrDA protocol support up to 115 Kbaud

– Up to 46 I/O, 5 V tolerant on 3.3 V

UPSD33xxV

A/D converter

– Eight channels, 10-bit resolution, 6 µs

Timers and interrupts

– Three 8032 standard 16-bit timers

– Programmable counter array (PCA), six 16-

bit modules for PWM/CAPCOM/timers

– 8/10/16-bit PWM operation

– 11 interrupt sources with two external

interrupt pins

Operating voltage source (±10%)

– 5 V devices use both 5.0 V and 3.3 V

– 3.3 V devices use only 3.3 V source

■

Table 1.

Device summary

Reference

UPSD33xx

UPSD3312DV, UPSD3333DV, UPSD3334DV, UPSD3354DV

Part number

UPSD3312D, UPSD3333D, UPSD3334D, UPSD3354D

May 2009

Doc ID 9685 Rev 7

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www.st.com

Contents

UPSD33xx

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

UPSD33xx hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1

Internal memory (MCU, standard 8032 memory: DATA, IDATA, SFR) . . . 29

4.1.1

4.1.2

4.1.3

DATA memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

IDATA memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SFR memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2

External memory (PSD module: program memory, data memory) . . . . . 29

4.2.1

4.2.2

4.2.3

Program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Memory placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8032 MCU core performance enhancements . . . . . . . . . . . . . . . . . . . . 32

5.1

5.2

5.3

Pre-Fetch Queue (PFQ) and Branch Cache (BC) . . . . . . . . . . . . . . . . . . 33

PFQ example, multi-cycle instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Aggregate performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

MCU module description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8032 MCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1

7.2

7.3

7.4

7.5

7.6

7.7

Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

B register (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

General purpose registers (R0 - R7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Program Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.7.1

7.7.2

7.7.3

Carry flag (CY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Auxiliary Carry flag (AC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

General purpose flag (F0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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7.7.4

7.7.5

7.7.6

Contents

Overflow flag (OV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Parity flag (P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Special function registers (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8032 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

9.10

9.11

Direct addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Immediate addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

External direct addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

External indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Indexed addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Absolute addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Long addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Bit addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

UPSD33xx instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Dual data pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.1

11.2

Data Pointer Control register, DPTC (85h) . . . . . . . . . . . . . . . . . . . . . . . . 56

Data Pointer Mode register, DPTM (86h) . . . . . . . . . . . . . . . . . . . . . . . . . 57

11.2.1

Firmware example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Debug unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

13.1

Individual interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

13.1.1

13.1.2

13.1.3

13.1.4

13.1.5

13.1.6

External interrupts Int0 and Int1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Timer 0 and 1 overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Timer 2 overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

UART0 and UART1 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

SPI interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

C interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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13.1.7

13.1.8

UPSD33xx

ADC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

PCA interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

MCU clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

14.1

14.2

MCU_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

PERIPH_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

14.2.1

JTAG interface clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

15.1

15.2

15.3

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Reduced frequency mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Oscillator and external components . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

I/O ports of MCU module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

17.1

MCU port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

17.1.1

17.1.2

17.1.3

17.1.4

GPIO function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

GPIO output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

GPIO input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

18.1

18.2

18.3

Bus read cycles (PSEN or RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Bus write cycles (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Controlling the PFQ and BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Supervisory functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

19.1

19.2

19.3

19.4

19.5

External reset input pin, RESET_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Low V

voltage detect, LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Power-up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

JTAG debug Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Watchdog timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

19.5.1

Firmware example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Standard 8032 timer/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

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20.1

20.2

20.3

20.4

20.5

Standard timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

SFR, TCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

SFR, TMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Timer 0 and Timer 1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

20.5.1

20.5.2

20.5.3

20.5.4

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

20.6

Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

20.6.1

20.6.2

20.6.3

Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Auto-reload mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Baud rate generator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Serial UART interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

21.1

UART operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

21.1.1

21.1.2

21.1.3

21.1.4

21.1.5

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Multiprocessor communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

21.2

21.3

Serial port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

UART baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

21.3.1

21.3.2

Using Timer 1 to generate baud rates . . . . . . . . . . . . . . . . . . . . . . . . . 110

Using Timer/Counter 2 to generate baud rates . . . . . . . . . . . . . . . . . . 111

21.4

21.5

21.6

More about UART mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

More about UART mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

More about UART modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

IrDA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

22.1

Pulse width selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

23.1

23.2

23.3

I2C interface main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

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