ATSAMS70N21A-CFNT datasheet, PDF

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> ATSAMS70N21A-CFNT

ATSAMS70N21A-CFNT: DescriptionIC MCU 32BIT 2MB FLASH 100VFBGA; CategoryThe embedded processor and controller Microcontrollers and processors; File Size17MB，2248 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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ATSAMS70N21A-CFNT Overview

IC MCU 32BIT 2MB FLASH 100VFBGA

ATSAMS70N21A-CFNT Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microchip
package instruction	VFBGA-100
Reach Compliance Code	compliant
Factory Lead Time	6 weeks
Has ADC	YES
Address bus width
bit size	32
maximum clock frequency	20 MHz
DAC channel	YES
DMA channel	YES
External data bus width
JESD-30 code	S-PBGA-B100
JESD-609 code	e1
length	7 mm
Number of I/O lines	75
Number of terminals	100
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	SQUARE
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
ROM programmability	FLASH
Maximum seat height	1 mm
speed	300 MHz
Maximum supply voltage	1.32 V
Minimum supply voltage	1.08 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.65 mm
Terminal location	BOTTOM
width	7 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC
Base Number Matches	1

User Manual

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SAM E70/S70/V70/V71 Family

32-bit ARM Cortex-M7 MCUs with FPU, Audio and

Graphics Interfaces, High-Speed USB, Ethernet, and

Advanced Analog

Features

Core

•

ARM Cortex -M7 running at up to 300 MHz

16 Kbytes of I-Cache and 16 Kbytes of D-Cache with Error Code Correction (ECC)

Single-precision and double-precision HW Floating Point Unit (FPU)

Memory Protection Unit (MPU) with 16 zones

DSP Instructions, Thumb -2 Instruction Set

Embedded Trace Module (ETM) with instruction trace stream, including Trace Port Interface Unit

(TPIU)

Memories

•

Up to 2048 Kbytes embedded Flash with unique identifier and user signature for user-defined data

•

Up to 384 Kbytes embedded Multi-port SRAM

•

Tightly Coupled Memory (TCM)

•

16 Kbytes ROM with embedded Bootloader routines (UART0, USB) and IAP routines

•

16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR and

NAND Flash with on-the-fly scrambling

•

16-bit SDRAM Controller (SDRAMC) interfacing up to 256 MB and with on-the-fly scrambling

System

•

Embedded voltage regulator for single-supply operation

•

Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog for safe operation

•

Quartz or ceramic resonator oscillators: 3 MHz to 20 MHz main oscillator with failure detection, 12

MHz or 16 MHz needed for USB operations. Optional low-power 32.768 kHz for RTC or device

clock

•

RTC with Gregorian calendar mode, waveform generation in low-power modes

•

RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency variations

•

32-bit low-power Real-time Timer (RTT)

•

High-precision Main RC oscillator with 12 MHz default frequency.

•

32.768 kHz crystal oscillator or Slow RC oscillator as source of low-power mode device clock

(SLCK)

•

One 500 MHz PLL for system clock, one 480 MHz PLL for USB high-speed operations

•

Temperature Sensor

•

One dual-port 24-channel central DMA Controller (XDMAC)

2018 Microchip Technology Inc.

Datasheet

DS60001527C-page 1

SAM E70/S70/V70/V71 Family

Low-Power Features

•

Low-power sleep, wait and backup modes, with typical power consumption down to 1.1 μA in Backup

mode with RTC, RTT and wakeup logic enabled

•

Ultra low-power RTC and RTT

•

1 Kbyte of backup RAM (BRAM) with dedicated regulator

Peripherals

•

One Ethernet MAC (GMAC) 10/100 Mbps in MII mode and RMII with dedicated DMA. IEEE1588 PTP

frames and 802.3az Energy-efficiency support. Ethernet AVB support with IEEE802.1AS Timestamping

and IEEE802.1Qav credit-based traffic-shaping hardware support.

•

USB 2.0 Device/Mini Host High-speed (USBHS) at 480 Mbps, 4-Kbyte FIFO, up to 10 bidirectional

endpoints, dedicated DMA

12-bit ITU-R BT. 601/656 Image Sensor Interface (ISI)

Two master Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD) with SRAM-based

mailboxes, time-triggered and event-triggered transmission

MediaLB device with 3-wire mode, up to 1024 x Fs speed, supporting MOST25 and MOST50

networks

Three USARTs, USART0, USART1, USART2, support LIN mode, ISO7816, IrDA , RS-485, SPI,

Manchester and Modem modes; USART1 supports LON mode.

™

Five 2-wire UARTs with SleepWalking support

Three Two-Wire Interfaces (TWIHS) (I

C-compatible) with SleepWalking support

Quad I/O Serial Peripheral Interface (QSPI) interfacing up to 256 MB Flash and with eXecute-In-Place

and on-the-fly scrambling

Two Serial Peripheral Interfaces (SPI)

One Serial Synchronous Controller (SSC) with I

S and TDM support

Two Inter-IC Sound Controllers (I2SC)

One High-speed Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC)

Four Three-Channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes,

constant on time. Quadrature decoder logic and 2-bit Gray Up/Down Counter for stepper motor

Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and eight fault inputs

per PWM for motor control, two external triggers to manage power factor correction (PFC), DC-DC and

lighting control.

Two Analog Front-End Controllers (AFEC), each supporting up to 12 channels with differential input

mode and programmable gain stage, allowing dual sample-and-hold (S&H) at up to 1.7 Msps. Offset

and gain error correction feature.

One 2-channel, 12-bit, 1 Msps-per-channel Digital-to-Analog Controller (DAC) with Differential and

Over Sampling modes

One Analog Comparator Controller (ACC) with flexible input selection, selectable input hysteresis

•

Cryptography

•

True Random Number Generator (TRNG)

•

AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications

•

Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and SHA256.

I/O

•

Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch

filtering and On-die Series Resistor Termination

Five Parallel Input/Output Controllers (PIO)

2018 Microchip Technology Inc.

Datasheet

DS60001527C-page 2

SAM E70/S70/V70/V71 Family

Table of Contents

Features.......................................................................................................................... 1

1. Configuration Summary...........................................................................................15

2. Ordering Information................................................................................................17

3. Block Diagram......................................................................................................... 18

4. Signal Description....................................................................................................22

5. Automotive Quality Grade....................................................................................... 31

6. Package and Pinout................................................................................................ 32

6.1.

6.2.

6.3.

6.4.

6.5.

6.6.

144-lead Packages.....................................................................................................................32

144-lead Package Pinout........................................................................................................... 33

100-lead Packages.....................................................................................................................39

100-lead Package Pinout........................................................................................................... 40

64-lead Package........................................................................................................................ 44

64-lead Package Pinout............................................................................................................. 44

7. Power Considerations............................................................................................. 48

7.1.

7.2.

7.3.

7.4.

7.5.

7.6.

7.7.

7.8.

Power Supplies.......................................................................................................................... 48

Power Constraints...................................................................................................................... 48

Voltage Regulator.......................................................................................................................50

Backup SRAM Power Switch..................................................................................................... 50

Active Mode................................................................................................................................50

Low-power Modes...................................................................................................................... 50

Wakeup Sources........................................................................................................................ 52

Fast Startup................................................................................................................................53

8. Input/Output Lines................................................................................................... 54

8.1.

8.2.

8.3.

8.4.

General-Purpose I/O Lines.........................................................................................................54

System I/O Lines........................................................................................................................ 54

NRST Pin................................................................................................................................... 56

ERASE Pin................................................................................................................................. 56

9. Interconnect.............................................................................................................57

10. Product Mapping..................................................................................................... 58

11. Memories.................................................................................................................59

11.1. Embedded Memories................................................................................................................. 59

11.2. External Memories..................................................................................................................... 65

12. Event System.......................................................................................................... 66

2018 Microchip Technology Inc.

Datasheet

DS60001527C-page 4

SAM E70/S70/V70/V71 Family

12.1. Embedded Characteristics......................................................................................................... 66

12.2. Real-time Event Mapping........................................................................................................... 67

13. System Controller.................................................................................................... 71

13.1. System Controller and Peripherals Mapping..............................................................................71

13.2. Power-on-Reset, Brownout and Supply Monitor........................................................................ 71

13.3. Reset Controller......................................................................................................................... 71

14. Peripherals.............................................................................................................. 73

14.1. Peripheral Identifiers.................................................................................................................. 73

14.2. Peripheral Signal Multiplexing on I/O Lines................................................................................76

15. ARM Cortex-M7 (ARM)........................................................................................... 77

15.1. ARM Cortex-M7 Configuration................................................................................................... 77

16. Debug and Test Features........................................................................................ 78

16.1.

16.2.

16.3.

16.4.

16.5.

16.6.

16.7.

Description................................................................................................................................. 78

Embedded Characteristics......................................................................................................... 78

Associated Documents...............................................................................................................78

Debug and Test Block Diagram..................................................................................................79

Debug and Test Pin Description................................................................................................. 79

Application Examples................................................................................................................. 80

Functional Description................................................................................................................81

17. SAM-BA Boot Program............................................................................................86

17.1.

17.2.

17.3.

17.4.

17.5.

17.6.

Description................................................................................................................................. 86

Embedded Characteristics......................................................................................................... 86

Hardware and Software Constraints.......................................................................................... 86

Flow Diagram............................................................................................................................. 86

Device Initialization.....................................................................................................................87

SAM-BA Monitor.........................................................................................................................87

18. Fast Flash Programming Interface (FFPI)............................................................... 92

18.1. Description................................................................................................................................. 92

18.2. Embedded Characteristics......................................................................................................... 92

18.3. Parallel Fast Flash Programming............................................................................................... 92

19. Bus Matrix (MATRIX).............................................................................................101

19.1.

19.2.

19.3.

19.4.

Description............................................................................................................................... 101

Embedded Characteristics....................................................................................................... 101

Functional Description..............................................................................................................103

Register Summary....................................................................................................................109

20. USB Transmitter Macrocell Interface (UTMI).........................................................132

20.1. Description............................................................................................................................... 132

20.2. Embedded Characteristics....................................................................................................... 132

20.3. Register Summary....................................................................................................................133

2018 Microchip Technology Inc.

Datasheet

DS60001527C-page 5

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