ZETA-915-D datasheet, PDF - EEWORLD Datasheet

ZETA-915-D: DescriptionRF TRANSCEIVER MODULE DIL +13DBM; CategoryTopical application Wireless rf/communication; File Size4MB，13 Pages; ManufacturerRF Solutions; Websitehttps://www.rfsolutions.co.uk/; Environmental Compliance

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RF TRANSCEIVER MODULE DIL +13DBM

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ZETA-915-D Related Products

	ZETA-915-D	ZETA-868-D	ZETA-433-D	ZETA-433-SO	ZETA-868-SO	ZETA-915-SO
Description	RF TRANSCEIVER MODULE DIL +13DBM	RF TRANSCEIVER MODULE DIL +13DBM	RF TRANSCEIVER MODULE DIL +13DBM	RF TXRX MODULE ISM<1GHZ	RF TXRX MODULE ISM<1GHZ	RF TXRX MODULE ISM<1GHZ
frequency	915MHz	868MHz	433MHz	433MHz	868MHz	915MHz
data rate	500kbps	500kbps	500kbps	500kbps	500kbps	500kbps
Power - output	13dBm	13dBm	13dBm	13dBm	13dBm	13dBm
Sensitivity	-116dBm	-116dBm	-116dBm	-116dBm	-116dBm	-116dBm
serial interface	SPI	SPI	SPI	SPI	SPI	SPI
IC/parts used	Si4455	Si4455	Si4455	Si4455	Si4455	Si4455
Voltage - Power	1.8 V ~ 3.6 V	1.8 V ~ 3.6 V	1.8 V ~ 3.6 V	1.8 V ~ 3.6 V	1.8 V ~ 3.6 V	1.8 V ~ 3.6 V
Current - Receive	10mA	10mA	10mA	10mA	10mA	10mA
Current - Transmission	30mA	30mA	30mA	18mA ~ 30mA	18mA ~ 30mA	18mA ~ 30mA
Installation type	surface mount	surface mount	surface mount	surface mount	surface mount	surface mount
Operating temperature	-40°C ~ 85°C	-40°C ~ 85°C	-40°C ~ 85°C	-40°C ~ 85°C	-40°C ~ 85°C	-40°C ~ 85°C
Package/casing	12-SMD module	12-SMD module	12-SMD module	12-SMD module	12-SMD module	12-SMD module

Is the baud rate for communication between microcontrollers set in advance? Or calculated? Also, why does the crystal oscillator have 11.0592...: Is the baud rate for communication between microcontrollers set in advance? Or calculated? Also, why does the crystal oscillator havea value of 11.0592M? Common frequencies are 4M, 8M, 12M, 16M, and 2...; QWE4562009 MCU

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FPGA Getting Started ABCs: Coding Style: [if gte mso 9]>Normal07.8 磅02falsefalsefalseMicrosoftInternetExplorer4Let me say a few words off topic first. Regarding the code style part, I tried very hard to write this part well. I revised it 4 t...; tx_xy FPGA/CPLD

can't open Verilog Design File: Error (10054): Verilog HDL File I/O error at moire_data.v(9): can't open Verilog Design File "E:kaifabanFPGAprojectmoire_datamoire_data1.txt" The above error always occurs when compiling. The file to ...; yjm19860704 FPGA/CPLD

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