PRELIMINARY DATA SHEET
µ
PD72870,72871
IEEE1394 1-CHIP OHCI HOST CONTROLLER
MOS INTEGRATED CIRCUIT
The
µ
PD72870, 72871 are the LSIs which integrated OHCI-Link and PHY function into a single chip.
The
µ
PD72870, 72871 comply with the P1394a draft 2.0 specifications and the OpenHCI IEEE1394 1.0 and work
up to 400 Mbps.
These make design so compact for PC and PC card application.
FEATURES
• Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0
• Compliant with Physical Layer Services as defined in P1394a draft 2.0 (Data Rate 100/200/400 Mbps)
3-port :
µ
PD72870
1-port :
µ
PD72871
• Compliant with protocol enhancement as defined in P1394a draft 2.0
• Modular 32-bit host interface compliant to PCI Specification release 2.1
• Support PCI-Bus Power Management Interface Specification release 1.0
• Modular 32-bit host interface compliant to Card Bus Specification
• Cycle Master and Isochronous Resource Manager capable
5
• Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048
bytes)
• 32-bit CRC generation and checking for receive/transmit packets
• 4 isochronous transmit DMAs and 4 isochronous receive DMAs supported
• 32-bit DMA channels for physical memory read/write
• Clock generation by 24.576 MHz X’tal
• Internal control and operational registers direct-mapped to PCI configuration space
• 2-wire Serial EEPROM
TM
interface supported
• Separate power supply Link and PHY
ORDERING INFORMATION
Part number
Package
160-pin plastic LQFP (Fine pitch) (24 x 24 mm)
192-pin Plastic FBGA (14 x 14 mm)
160-pin plastic LQFP (Fine pitch) (24 x 24 mm)
192-pin Plastic FBGA (14 x 14 mm)
µ
PD72870GM-8ED
µ
PD72870F1-FA2
µ
PD72871GM-8ED
µ
PD72871 F1-FA2
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S13925EJ2V0DS00 (2nd edition)
Date Published September 1999 NS CP(K)
Printed in Japan
The mark
5
shows major revised points.
1999
µ
PD72870,72871
Link Block Diagram
Serial ROM Interface
PCI Bus / Cardbus Interface
PCI Controller Interface
(Master, Parity Check & Generator)
Byte
Buf
Swap
PCI-DMA
IOREG
CSR
(CIS)
PFCOMM
Byte
Swap
ATF
Byte
Swap
ITF
PCICFG
ATDMA
PAU
GRSU
ITCF
Byte
RF
Swap
Link Layer
Core
OPCIBUS_ARB
GRQU
ITDMA
IRDMA0-
IRDMA3
SFIDU
RCF
IOREG
ATDMA
ATF
CIS
CSR
IOREG
IRDMA
ITCF
ITDMA
ITF
OPCIBUS_ARB
PAU
PCICFG
PCIS_CNT
PFCOMM
RCF
RF
SFIDU
: Asynchronous Transmit DMA
: Asynchronous Transmit FIFO
: CIS Register
: Control and Status Registers
: IO Registers
: Isochronous Receive DMA
: Isochronous Transmit Control FIFO
: Isochronous Transmit DMA
: Isochronous Transmit FIFO
: OPCI Internal Bus Arbitration
: Physical Response and Request Unit
: PCI Configuration Registers
: PHY Control Isochronous Control
: Pre Fetch Command FIFO
: Receive Control FIFO
: Receive FIFO
: Self-ID DMA
4
Preliminary Data Sheet S13925EJ2V0DS00
PHY/Link Interface
OPCI Internal Bus
PCIS Bus (PCI Slave Bus)
PCIS_CNT