DATA SHEET
µ
PD488448 for Rev. P
128 M-bit Direct Rambus™ DRAM
MOS INTEGRATED CIRCUIT
Description
The Direct Rambus DRAM (Direct RDRAM
™
) is a general purpose high-performance memory device suitable for
use in a broad range of applications including computer memory, graphics, video, and any other application where
high bandwidth and low latency are required.
The
µ
PD488448 is 128M-bit Direct Rambus DRAM (RDRAM
®
), organized as 8M words by 16 bits.
The use of Rambus Signaling Level (RSL) technology permits 600 MHz to 800 MHz transfer rates while using
conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers
at 1.25 ns per two bytes (10 ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and data buses with independent row and column control
yield over 95% bus efficiency. The Direct RDRAM’s thirty-two banks support up to four simultaneous transactions.
System oriented features for mobile, graphics and large memory systems include power management, byte
masking.
The
µ
PD488448 is offered in a CSP horizontal package suitable for desktop as well as low-profile add-in card and
mobile applications. Direct RDRAMs operate from a 2.5 volt supply.
Features
•
Highest sustained bandwidth per DRAM device
- 1.6 GB/s sustained data transfer rate
- Separate control and data buses for maximized efficiency
- Separate row and column control buses for easy scheduling and highest performance
- 32 banks: four transactions can take place simultaneously at full bandwidth data rates
•
Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
•
Advanced power management:
- Multiple low power states allows flexibility in power consumption versus time to transition to active state
- Power-down self-refresh
•
Overdrive current mode
•
Organization: 1 Kbyte pages and 32 banks, x 16
•
Uses Rambus Signaling Level (RSL) for up to 800 MHz operation
•
Package : 62-pin TAPE FBGA (
µ
BGA
®
) and 62-pin PLASTIC FBGA (D BGA
™
(Die Dimension Ball Grid Array) )
2
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14837EJ3V0DS00 (3rd edition)
Date Published August 2000 NS CP (K)
Printed in Japan
The mark
•
shows major revised points.
©
2000
µ
PD488448 for Rev. P
Pin Description
Signal
SIO0, SIO1
Input / Output
Type
#pins
2
Description
Serial input/output. Pins for reading from and writing to the control registers using
a serial access protocol. Also used for power management.
CMD
Input
CMOS
Note1
1
Command input. Pins used in conjunction with SIO0 and SIO1 for reading from
and writing to the control registers. Also used for power management.
SCK
Input
CMOS
Note1
1
Serial clock input. Clock source used for reading from and writing to the control
registers.
V
DD
V
DDa
V
CMOS
GND
GND
a
DQA7..DQA0
Input / Output
RSL
Note2
10
1
2
13
1
8
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Eight pins which carry a byte of read or write data between the
Channel and the RDRAM.
CFM
Input
RSL
Note2
Input / Output CMOS
Note1
1
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
CFMN
Input
RSL
Note2
1
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
V
REF
CTMN
Input
RSL
Note2
1
1
Logic threshold reference voltage for RSL signals.
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
CTM
Input
RSL
Note2
1
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Positive polarity.
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
DQB7..DQB0
Input
RSL
Note2
3
Row access control. Three pins containing control and address information for
row accesses.
Input
RSL
Note2
5
Column access control. Five pins containing control and address information for
column accesses.
Input / Output
RSL
Note2
8
Data byte B. Eight pins which carry a byte of read or write data between the
Channel and the RDRAM.
NC
Total pin count per package
2
62
These pins aren’t connected to inside of the chip.
Notes 1.All
CMOS signals are high-true ; a high voltage is a logic one and a low voltage is logic zero.
2.All
RSL signals are low-true ; a low voltage is a logic one and a high voltage is logic zero.
Data Sheet M14837EJ3V0DS00
5
Microcontroller MCU
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