PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4664312-X
64M-BIT CMOS MOBILE SPECIFIED RAM
4M-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
Description
The
µ
PD4664312-X is a high speed, low power, 67,108,864 bits (4,194,304 words by 16 bits) CMOS Mobile
Specified RAM featuring Low Power Static RAM compatible function and pin configuration.
The
µ
PD4664312-X is fabricated with advanced CMOS technology using one-transistor memory cell.
The
µ
PD4664312-X is packed in 93-pin TAPE FBGA.
Features
•
4,194,304 words by 16 bits organization
•
Fast access time: 65, 75 ns (MAX.)
•
Fast page access time: 18, 25 ns (MAX.)
•
Byte data control: /LB (I/O0 to I/O7), /UB (I/O8 to I/O15)
•
Low voltage operation: 2.7 to 3.1 V (-B65X)
2.7 to 3.1 V (Chip), 1.65 to 2.1 V (I/O) (-BE75X)
•
Operating ambient temperature: T
A
= –25 to +85 °C
•
Output Enable input for easy application
•
Chip Enable input: /CS pin
•
Standby Mode input: MODE pin
•
Standby Mode1: Normal standby (Memory cell data hold valid)
•
Standby Mode2: Density of memory cell data hold is variable
µ
PD4664312
Access
time
ns (MAX.)
Chip
-B65X
-BE75X
Note
65
75
2.7 to 3.1
Operating supply
voltage
V
I/O
–
Operating
ambient
temperature
°C
–25 to +85
45
40
At operating
mA (MAX.)
Supply current
At standby
µ
A (MAX.)
Density of data hold
64M bits 16M bits 8M bits 4M bits
100
60
50
45
0M bit
10
2.7 to 3.1 1.65 to 2.1
Note
Under development
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15867EJ5V0DS00 (5th edition)
Date Published August 2002 NS CP (K)
Printed in Japan
The mark
shows major revised points.
©
2001
µ
PD4664312-X
Pin Configurations
/xxx indicates active low signal.
93-pin TAPE FBGA (12 x 9)
[
µ
PD4664312F9-B65X-CR2 ]
Top View
Bottom View
10
9
8
7
6
5
4
3
2
1
A BCDE FGH J K LM N P
P NM L K J HGF EDCBA
Top View
A
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
B
NC
NC
C
NC
NC
NC
A11
A8
/WE
NC
/LB
A7
NC
A15
A12
A19
MODE
NC
/UB
A6
A3
A21
A13
A9
A20
NC
A18
A5
A2
D
E
F
G
NC
NC
A14
A10
NC
NC
A17
A4
A1
NC
H
NC
A16
NC
I/O6
NC
NC
I/O1
GND
A0
NC
NC
I/O15
I/O13
I/O4
I/O3
I/O9
/OE
NC
GND
I/O7
I/O12
V
CC
NC
I/O10
I/O0
/CS
I/O14
I/O5
NC
I/O11
I/O2
I/O8
NC
NC
NC
NC
NC
NC
NC
NC
J
K
L
M
NC
NC
NC
N
NC
NC
P
NC
A0 to A21
/CS
MODE
/WE
/OE
: Address inputs
: Chip Select
: Standby mode
: Write enable
: Output enable
/LB, /UB
V
CC
GND
NC
Note
: Byte data select
: Power supply
: Ground
: No Connection
I/O0 to I/O15 : Data inputs / outputs
Note
Some signals can be applied because this pin is not internally connected.
Remarks
Refer to
Package Drawing
for the index mark.
Preliminary Data Sheet M15867EJ5V0DS
3
µ
PD4664312-X
93-pin TAPE FBGA (12 x 9)
[
µ
PD4664312F9-BE75X-CR2 ]
Top View
Bottom View
10
9
8
7
6
5
4
3
2
1
A BCDE FGH J K LM N P
P NM L K J HGF EDCBA
Top View
A
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
B
NC
NC
C
NC
NC
NC
A11
A8
/WE
NC
/LB
A7
NC
A15
A12
A19
MODE
NC
/UB
A6
A3
A21
A13
A9
A20
NC
A18
A5
A2
D
E
F
G
NC
NC
A14
A10
NC
NC
A17
A4
A1
NC
H
NC
A16
NC
I/O6
NC
NC
I/O1
GND
A0
NC
NC
I/O15
I/O13
I/O4
I/O3
I/O9
/OE
NC
GND
I/O7
I/O12
V
CC
NC
I/O10
I/O0
/CS
I/O14
I/O5
V
CC
Q
I/O11
I/O2
I/O8
NC
NC
NC
NC
NC
NC
NC
NC
J
K
L
M
NC
NC
NC
N
NC
NC
P
NC
A0 to A21
/CS
MODE
/WE
/OE
: Address inputs
: Chip Select
: Standby mode
: Write enable
: Output enable
/LB, /UB
V
CC
V
CC
Q
GND
NC
Note
: Byte data select
: Power supply
: Input / Output power supply
: Ground
: No Connection
I/O0 to I/O15 : Data inputs / outputs
Note
Some signals can be applied because this pin is not internally connected.
Remarks
Refer to
Package Drawing
for the index mark.
4
Preliminary Data Sheet M15867EJ5V0DS
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