U62256A
Standard 32K x 8 SRAM
Features
!
32768x8 bit static CMOS RAM
!
Access times 70 ns, 100 ns
!
Common data inputs and
Description
The U62256A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
the outputs DQ0-DQ7. After the
address change, the data outputs
go High-Z until the new information
read is available. The data outputs
have not preferred state.
The Read cycle is finished by the
falling edge of W, or by the rising
edge of E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
data outputs
!
Three-state outputs
!
Typ. operating supply current
70 ns: 50 mA
100 ns: 40 mA
!
TTL/CMOS-compatible
!
Automatical reduction of power
dissipation in long Read Cycles
!
Power supply voltage 5 V + 10 %
!
Operating temperature ranges
0 to 70 °C
-40 to 85 °C
-40 to 125 °C
!
QS 9000 Quality Standard
!
ESD protection > 2000 V
(MIL STD 883C M3015.7)
!
Latch-up immunity >100 mA
!
Packages: PDIP28 (600 mil)
SOP28 (330 mil)
Pin Configuration
Pin Description
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
20
19
18
17
16
15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
PDIP
SOP
21
Top View
April 20, 2004
1
U62256A
Block Diagram
A6
A7
A8
A9
A10
A11
A12
A13
A14
Row Address
Inputs
Row Decoder
Memory Cell
Array
512 Rows x
64 x 8 Columns
Common Data I/O
A0
A1
A2
A3
A4
A5
Column Address
Inputs
Column Decoder
DQ0
Sense Amplifier/
Write Control Logic
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Address
Change
Detector
Clock
Generator
V
CC
V
SS
E
W
G
Truth Table
Operating Mode
Standby/not selected
Internal Read
Read
Write
* H or L
E
H
L
L
L
W
*
H
H
L
G
*
H
L
*
DQ0 - DQ7
High-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
2
April 20, 2004
U62256A
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured ±200 mV from steady-state voltage.
Absolute Maximum Ratings
a
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
C-Type
K-Type
A-Type
C/K-Type
A-Type
Symbol
V
CC
V
I
V
O
P
D
T
a
Min.
-0.5
-0.5
-0.5
-
0
-40
-40
-65
-65
Max.
7
V
CC
+ 0.5
b
V
CC
+ 0.5
b
1
70
85
125
125
150
200
Unit
V
V
V
W
°C
Storage Temperature
Output Short-Circuit Current
at V
CC
= 5 V and V
O
= 0 V
c
a
T
stg
°C
| I
OS
|
mA
b
c
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability
Maximum voltage is 7 V
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Recommended
Operating Conditions
Power Supply Voltage
Input Low Voltage
d
Input High Voltage
d
Symbol
V
CC
V
IL
V
IH
Conditions
Min.
4.5
-0.3
2.2
Max.
5.5
0.8
V
CC
+ 0.3
Unit
V
V
V
-2 V at Pulse Width 10 ns
April 20, 2004
3
U62256A
Electrical Characteristics
Supply Current - Operating Mode
Symbol
I
CC(OP)
V
CC
V
IL
V
IH
t
cW
t
cW
V
CC
V
E
C-Type
K-Type
A-Type
V
CC
V
E
V
CC
I
OH
V
CC
I
OL
V
CC
V
IH
V
CC
V
IL
V
CC
V
OH
V
CC
V
OL
V
CC
V
OH
V
CC
V
OL
Conditions
=
=
=
=
=
5.5 V
0.8 V
2.2 V
70 ns
100 ns
Min.
Max.
Unit
70
65
mA
mA
Supply Current - Standby Mode
(CMOS level)
I
CC(SB)
= 5.5 V
= V
CC
- 0.2 V
5
10
50
µA
µA
µA
Supply Current - Standby Mode
(TTL level)
Output High Voltage
Output Low Voltage
Input High Leakage Current
Input Low Leakage Current
Output High Current
Output Low Current
Output Leakage Current
High at Three-State Outputs
Low at Three-State Outputs
I
CC(SB)1
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
= 5.5 V
= 2.2 V
= 4.5 V
= -1.0 mA
= 4.5 V
= 3.2 mA
= 5.5 V
= 5.5 V
= 5.5 V
= 0V
=
=
=
=
4.5 V
2.4 V
4.5 V
0.4 V
2.4
1
mA
V
0.4
2
-2
-1
3,2
V
µA
µA
mA
mA
I
OHZ
I
OLZ
= 5.5 V
= 5.5 V
= 5.5 V
= 0V
1
-1
µA
µA
4
April 20, 2004
U62256A
Switching Characteristics
Read Cycle
Read Cycle Time
Address Access Time to Data Valid
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Z
G HIGH to Output in High-Z
E LOW to Output in Low-Z
G LOW to Output in Low-Z
Output Hold Time from Address Change
Symbol
Alt.
t
RC
t
AA
t
ACE
t
OE
t
HZCE
t
HZOE
t
LZCE
t
LZOE
t
OH
IEC
t
cR
t
a(A)
t
a(E)
t
a(G)
t
dis(E)
t
dis(G)
t
en(E)
t
en(G)
t
v(A)
5
0
5
Min.
70
70
70
35
25
25
5
0
5
07
Max.
Min.
100
100
100
45
35
35
10
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
Write Cycle
Write Cycle Time
Write Pulse Width
Write Pulse Width Setup Time
Address Setup Time
Address Valid to End of Write
Chip Enable Setup Time
Pulse Width Chip Enable to End of Write
Data Setup Time
Data Hold Time
Address Hold from End of Write
W LOW to Output in High-Z
G HIGH to Output in High-Z
W HIGH to Output in Low-Z
G LOW to Output in Low-Z
Symbol
Alt.
t
WC
t
WP
t
WP
t
AS
t
AW
t
CW
t
CW
t
DS
t
DH
t
AH
t
HZWE
t
HZOE
t
LZWE
t
LZOE
IEC
t
cW
t
w(W)
t
su(W)
t
su(A)
t
su(A-WH)
t
su(E)
t
w(E)
t
su(D)
t
h(D)
t
h(A)
t
dis(W)
t
dis(G)
t
en(W)
t
en(G)
0
0
Min.
70
55
55
0
65
65
65
30
0
0
07
Max.
Min.
100
70
70
0
80
80
80
35
0
0
25
25
0
0
10
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
35
ns
ns
ns
ns
April 20, 2004
5
ADI Reference Circuit
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