Note: Outputs shall be isolated from the chassis ground by at least 50 V
1
Minimum starting current for transient load response testing only. Unit is designed to operate and be within output regulation
at zero load.
DS1100TDC Data Sheet
Electrical Specifications
Protections
Main Output
Overcurrent protection
2
Overvoltage protection
1
Overtemperature protection
Fan fault protection
Standby Output
Overcurrent protection
3
Over-oltage protection
1
1
2
3
MIN
107%
13.5 V
NOM
MAX
130%
14.5 V
Yes, autorecovery
Yes
107%
3.6 V
150%
4.1V
Latch mode
Autorecovery for 5s then latch
Autorecovery
Control and Status Signals
Input Signals
PSON_L
Active LOW signal which enables/disables the main output. Pulling this signal LOW will turn-on the main output.
Recommended pull-up resistor to VSB is 5.1 kohms. A 100 pF decoupling capacitor is also recommended.
MIN
V
IL
V
IH
I
SOURCE
I
SINK
PSKILL_H
First break/last mate active HIGH signal which enables/disables the main output. This signal will have to be pulled to ground at the system side with a 100 ohm
resistor. A 100 pF decoupling capacitor is also recommended.
MIN
V
IL
V
IH
I
SOURCE
I
SINK
VSENSE+, VSENSE-
VSENSE+ and VSENSE- lines are the remote sense lines for regulation. Each line will compensate for a maximum of 200 mV.
Input logic level LOW
Input logic level HIGH
Current that may be sourced by this pin
Current that may be sunk by this pin at low state
2.0 V
MAX
0.8 V
3.6 V
4 mA
4 mA
Input logic level LOW
Input logic level HIGH
Current that may be sourced by this pin
Current that may be sunk by this pin at low state
2.0 V
MAX
0.8 V
3.6V
4 mA
4 mA
I
2
C Addressing
A1 Pin
0
0
1
1
A0 Pin
0
1
0
1
PMBus (w/r)
B0/B1
B2/B3
B4/B5
B6/B7
Ordering Information
Model Number
Nominal Main Output
Standby Output
Airflow Direction
DS1100TDC-3
DS1100TDC-3-001
12 V
12 V
3.3 V @ 3 A
3.3 V @ 3 A
Std (forward)
Reverse
* For additional addressing options, please contact techsupport
DS1100TDC Data Sheet
Control and Status Signals
Output Signals
INPUT_OK
Signal used to indicate the presence of DC input to the power supply. A logic level HIGH will indicate that the DC input to the power supply is within the operating
range while a logic level LOW will indicate that input has been lost.
This is an open collector/drain output. This pin is pulled high by a 1 kohm resistor connected to 3.3 V inside the power supply. It is recommended that this pin be
connected to a 200 pF decoupling capacitor and pulled down by a 100 kohm resistor.
MIN
V
OH
V
OL
I
SOURCE
I
SINK
PWR_GOOD / PWOK
Signal used to indicate that main output voltage is within regulation range. The PWR_GOOD signal will be driven HIGH when the output voltage is valid and will be
driven LOW when the output falls below the under-voltage threshold.
This signal also gives an advance warning when there is an impending power loss due to loss of DC input or system shutdown request. More details in the Timing Section.
This is an open collector/drain output. This pin is pulled high by a 1 kohm resistor connected to 3.3 V inside the power supply. It is recommended that this pin be
connected to a 100 pF decoupling capacitor and pulled down by a 100 kohm resistor.
MIN
V
OH
V
OL
I
SOURCE
I
SINK
Output high voltage
Output low voltage
Output signal source current
Output signal sink current
2.4 V
MAX
3.6 V
0.4 V
2 mA
4 mA
Output high voltage
Output low voltage
Output signal source current
Output signal sink current
2.4 V
MAX
3.6 V
0.4 V
2 mA
4 mA
Output Signals
PS_PRESENT
Signal used to indicate to the system that a power supply is inserted in the power bay. This pin is connected via a 220 ohm resistor to the standby return in the
power supply. Recommended pull-up resistor to VSB is 5.1 kohms. A 100 pF decoupling capacitor is also recommended.
PS_INTERRUPT
Active low signal used by the power supply to indicate to the system that a change in power supply status has occurred. This event can be triggered by faults such
as OVP, OCP, OTP, and fan fault. This signal can be cleared by a CLEAR_FAULT command. Recommended pull-up resistor to VSB is 5.1 kohms. A 100 pF
decoupling capacitor is also recommended.
MIN
V
OH
V
OL
I
SOURCE
I
SINK
Output high voltage
Output low voltage
Current that may be sourced by this pin
Current that may be sunk by this pin at low state
2.4 V
MAX
3.6 V
0.4 V
4 mA
4 mA
DS1100TDC Data Sheet
Control and Status Signals
BUS Signals
ISHARE
Bus signal used by the power supply for active current sharing. All power supplies configured in the system for n+n sharing will refer to this bus voltage inorder to
load share.
Voltage Range
I
SHARE
Voltage
The range of this signal for active sharing will be up to 8.0 V, which corresponds to the maximum output current.
MIN
Input logic level LOW
Voltage at 50% load, stand-alone unit
Voltage at 0% load, stand-alone unit
I
SOURCE
SCL, SDA
Clock and data signals defined as per I
2
C requirements. These pins are pulled high internally to 3.3V by a 100kohm resistor. It is recommended that these pins be
pulled-up to a 2.2 kohm resistor to 3.3 V and a 200 pF decoupling capacitor at the system side.
VL
VH
Input logic level LOW
Input logic level HIGH
2.0 V
0.8 V
3.6 V
Current that may be sourced by this pin
7.75
3.85
0
MAX
8.25
4.15
1.0
4.0 mA
Note:
All signal noise levels are below 400 mVpk-pk from 0 - 100 MHz.
Electrical Specifications
LED Indicators
Two LEDs are used to indicate the power supply status.
Input LED
Color
No input to PSU
Input present, STBY ON, main output OFF
Main output ON
Power supply warning (hi-temp)
Power supply warning (slow fan)
Power supply failure (OVP, OTP, FAN FAULT)
Green
Off
On
On
On
On
On
Fail LED
Amber/Green
Off
Blinking Amber, at least 1 Hz
Green
Blinking Amber/Green, at 2:1 ratio, at least 1 Hz
Blinking Amber/Green, at 1:1 ratio, at least 1 Hz
Amber
Firmware Reporting And Monitoring
Accuracy Range
Output loading
Input voltage
Input current
Input power
Output voltage
Output current
Temperature
Fan speed
±0.8 A fixed error
±0.55 A fixed error
±5 W fixed error up to 120 W input
±2%
±5%
±5 °C across operating range
±250 RPM
±2%
5% to 20%
20% to 50%
±5%
±4%
±4%
50% to 100%
PMBus
Remote ON/OFF
YES
YES
DS1100TDC Data Sheet
Electrical Specifications
Timing Specifications
Description
T
sb_On
T
INPUT_OK_ON
T
sb_Vout
T
INPUT_On_Delay
T
PWOK_On
T
INPUT_OK_Delay
T
PWOK_Hold-up
T
Vout_Hold-up
T
sb_Hold-up
T
PWR_GOOD_Off
T
PSON_On_Delay
Delay from input being applied to standby output being within regulation
Delay from input being applied to INPUT_OK assertion
Delay from standby output to main output voltage being within regulation
Delay from input being applied to main output being within regulation
Delay from output voltages within regulation limits to PWOK asserted
Delay from loss of input to assertion of INPUT_OK
Delay from loss of input to deassertion of PWOK
Delay from loss of input to main output falling out of regulation
Delay from loss of input to standby output falling out of regulation
Delay from deassertion of PWOK to output falling out of regulation
Delay from PSON assertion to output being within regulation
100
Min
Max
2500
1500
1000
3000
1000
20
PWOK may deassert as soon as input loss is detected
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