DM74AS646 • DM74AS648 Octal Bus Transceiver and Register
October 1986
Revised July 2003
DM74AS646 • DM74AS648
Octal Bus Transceiver and Register
General Description
This device incorporates an octal bus transceiver and an
octal D-type register configured to enable multiplexed
transmission of data from bus to bus or internal register to
bus.
This bus transceiver features totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance third
state and increased high-logic-level drive provide this
device with the capability of being connected directly to and
driving the bus lines in a bus-organized system without
need for interface or pull-up components. It is particularly
attractive for implementing buffer registers, I/O ports, bidi-
rectional bus drivers, and working registers.
The registers in the DM74AS646, DM74AS648 are edge-
triggered D-type flip-flops. On the positive transition of the
clock (CAB or CBA), the input bus data is stored.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A LOW
input level selects real-time data, and a HIGH level selects
stored data. The select controls have a “make before
break” configuration to eliminate a glitch which would nor-
mally occur in a typical multiplexer during the transition
between stored and real-time data.
The enable G and direction control pins provide four modes
of operation; real-time data transfer from bus A to B, real-
time data transfer from bus B to A, real-time bus A and/or B
data transfer to internal storage, or internal store data
transfer to bus A or B.
When the enable G pin is LOW, the direction pin selects
which bus receives data. When the enable G pin is HIGH,
both buses become disabled yet their input function is still
enabled.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Functionally and pin-for-pin compatible with LS TTL
counterpart
s
3-STATE buffer-type outputs drive bus lines directly
Ordering Code:
Order Number
DM74AS646WM
DM74AS646NT
DM74AS648WM
DM74AS648NT
Package Number
M24B
N24C
M24B
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2003 Fairchild Semiconductor Corporation
DS006324
www.fairchildsemi.com
DM74AS646 • DM74AS648
Absolute Maximum Ratings
(Note 3)
Supply Voltage
Input Voltage
Control Inputs
I/O Ports
Operating Free Air Temperature Range
Storage Temperature Range
Typical
θ
JA
N Package
M Package
41.1
°
C/W
81.5
°
C/W
7V
5.5V
0
°
C to
+
70
°
C
7V
−
65
°
C to
+
150
°
C
Note 3:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLK
t
W
t
SU
t
H
T
A
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency
Width of Clock Pulse
Data Setup Time (Note 4)
Data Hold Time (Note 4)
Free Air Operating Temperature
HIGH
LOW
0
5
6
6
↑
0
↑
0
70
Parameter
Min
4.5
2
0.8
Nom
5
Max
5.5
Units
V
V
V
mA
mA
MHz
ns
ns
ns
ns
−
15
48
90
°
C
Note 4:
The (↑) arrow indicates the positive edge of the Clock is used for reference.
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25°C.
Symbol
V
IK
V
OH
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
V
OL
I
I
I
IH
I
IL
I
O
I
CC
LOW Level
Output Voltage
Input Current @ Max
Input Voltage
HIGH Level Input Current
LOW Level Input Current
Output Drive Current
Supply Current
(Note 5)
V
CC
=
5.5V, V
IL
=
0.4V
(Note 5)
V
CC
=
5.5V, V
O
=
2.25V
V
CC
=
5.5V
DM74AS646
Outputs HIGH
Outputs LOW
Outputs Disabled
Outputs HIGH
DM74AS648
Outputs LOW
Outputs Disabled
Note 5:
For I/O ports, the parameters I
IH
and I
IL
include the OFF-State current, I
OZH
and I
OZL
.
Conditions
V
CC
=
4.5V, I
I
= −18
mA
V
CC
=
4.5V, V
IL
=
Max
V
IH
=
Min
V
CC
=
4.5V, V
IL
=
Min
V
IH
=
2V, I
OL
=
Max
V
CC
=
5.5V
V
I
=
7V
V
I
=
5.5V
V
CC
=
5.5V, V
IH
=
2.7V
Control Inputs
A or B Ports
Control Inputs
A or B Ports
Control Inputs
A or B Ports
I
OH
=
Max
I
OH
= −3
mA
Min
2
2.4
V
CC
−
2
Typ
Max
−1.2
Units
V
V
3.2
V
CC
=
4.5V to 5.5V, I
OH
= −2
mA
0.35
0.5
0.1
0.1
20
70
−0.5
−0.75
V
mA
µA
mA
mA
−30
120
130
130
110
120
120
−112
195
211
211
185
195
195
mA
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