DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
April 1986
Revised November 2001
DM74LS373 • DM74LS374
3-STATE Octal D-Type Transparent Latches
and Edge-Triggered Flip-Flops
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the DM74LS373 are transparent D-
type latches meaning that while the enable (G) is HIGH the
Q outputs will follow the data (D) inputs. When the enable
is taken LOW the output will be latched at the level of the
data that was set up.
The eight flip-flops of the DM74LS374 are edge-triggered
D-type flip flops. On the positive transition of the clock, the
Q outputs will be set to the logic states that were set up at
the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the latches or flip-flops. That is, the old data can be
retained or new data can be entered even while the outputs
are OFF.
Features
s
Choice of 8 latches or 8 D-type flip-flops in a single
package
s
3-STATE bus-driving outputs
s
Full parallel-access for loading
s
Buffered control inputs
s
P-N-P inputs reduce D-C loading on data lines
Ordering Code:
Order Number
DM74LS373WM
DM74LS373SJ
DM74LS373N
DM74LS374WM
DM74LS374SJ
DM74LS374N
Package Number
M20B
M20D
N20A
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation
DS006431
www.fairchildsemi.com
DM74LS373 • DM74LS374
Connection Diagrams
DM74LS373
DM74LS374
Function Tables
DM74LS373
Output
Control
L
L
L
H
Enable
G
H
H
L
X
D
H
L
X
X
Output
H
L
Q
0
Z
Output
Control
L
L
L
H
DM74LS374
Clock
D
H
L
X
X
Output
H
L
Q
0
Z
↑
↑
L
X
H
=
HIGH Level (Steady State)
L
=
LOW Level (Steady State)
X
=
Don’t Care
Z
=
High Impedance State
↑ =
Transition from LOW-to-HIGH level
Q
0
=
The level of the output
before steady-state input conditions were established.
Logic Diagrams
DM74LS373
Transparent Latches
DM74LS374
Positive-Edge-Triggered Flip-Flops
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2
DM74LS373 • DM74LS374
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range
Operating Free Air Temperature Range
7V
7V
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
−
65
°
C to
+
150
°
C
0
°
C to
+
70
°
C
DM74LS373 Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
t
W
t
SU
t
H
T
A
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Pulse Width
(Note 3)
Enable HIGH
Enable LOW
15
15
5
↓
20
↓
0
70
Parameter
Min
4.75
2
0.8
Nom
5
Max
5.25
Units
V
V
V
mA
mA
ns
ns
ns
−
2.6
24
Data Setup Time (Note 2) (Note 3)
Data Hold Time (Note 2) (Note 3)
Free Air Operating Temperature
°
C
Note 2:
The symbol (↓) indicates the falling edge of the clock pulse is used for reference.
Note 3:
T
A
=
25°C and V
CC
=
5V.
DM74LS373 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CC
Input Current @ Max Input Voltage
HIGH Level Input Current
LOW Level Input Current
Off-State Output Current with
HIGH Level Output Voltage Applied
Off-State Output Current with
LOW Level Output Voltage Applied
Short Circuit Output Current
Supply Current
Conditions
V
CC
=
Min, I
I
= −18
mA
V
CC
=
Min, I
OH
=
Max
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max
V
IL
=
Max, V
IH
=
Min
I
OL
=
12 mA, V
CC
=
Min
V
CC
=
Max, V
I
=
7V
V
CC
=
Max, V
I
=
2.7V
V
CC
=
Max, V
I
=
0.4V
V
CC
=
Max, V
O
=
2.7V
V
IH
=
Min, V
IL
=
Max
V
CC
=
Max, V
O
=
0.4V
V
IH
=
Min, V
IL
=
Max
V
CC
=
Max (Note 5)
V
CC
=
Max, OC
=
4.5V,
D
n
, Enable
=
GND
Note 4:
All typicals are at V
CC
=
5V, T
A
=
25°C.
Note 5:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
Min
Typ
(Note 4)
Max
−1.5
Units
V
V
2.4
3.1
0.35
0.5
0.4
0.1
20
−0.4
20
−20
V
mA
µA
mA
µA
µA
mA
mA
−50
24
−225
40
3
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DM74LS373 • DM74LS374
DM74LS373 Switching Characteristics
at V
CC
=
5V and T
A
=
25°C
R
L
=
667Ω
Symbol
Parameter
From (Input)
To (Output)
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Output Enable Time
to HIGH Level Output
Output Enable Time
to LOW Level Output
Output Disable Time
from HIGH Level Output (Note 6)
Output Disable Time
from LOW Level Output (Note 6)
Note 6:
C
L
=
5 pF.
C
L
=
45 pF
Min
Max
18
18
30
30
28
36
20
25
C
L
=
150 pF
Min
Max
26
27
38
36
36
50
Units
Data to Q
Data to Q
Enable to Q
Enable to Q
Output Control to Any Q
Output Control to Any Q
Output Control to Any Q
Output Control to Any Q
ns
ns
ns
ns
ns
ns
ns
ns
DM74LS374 Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
t
W
t
SU
t
H
T
A
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Pulse Width
(Note 8)
Clock HIGH
Clock LOW
15
15
20
↑
1
↑
0
70
Parameter
Min
4.75
2
0.8
Nom
5
Max
5.25
Units
V
V
V
mA
mA
ns
ns
ns
−
2.6
24
Data Setup Time (Note 7) (Note 8)
Data Hold Time (Note 7) (Note 8)
Free Air Operating Temperature
°
C
Note 7:
The symbol (↑) indicates the rising edge of the clock pulse is used for reference.
Note 8:
T
A
=
25°C and V
CC
=
5V.
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4
DM74LS373 • DM74LS374
DM74LS374 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CC
Input Current @ Max Input Voltage
HIGH Level Input Current
LOW Level Input Current
Off-State Output Current with
HIGH Level Output Voltage Applied
Off-State Output Current with
LOW Level Output Voltage Applied
Short Circuit Output Current
Supply Current
Conditions
V
CC
=
Min, I
I
= −18
mA
V
CC
=
Min, I
OH
=
Max
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max
V
IL
=
Max, V
IH
=
Min
I
OL
=
12 mA, V
CC
=
Min
V
CC
=
Max, V
I
=
7V
V
CC
=
Max, V
I
=
2.7V
V
CC
=
Max, V
I
=
0.4V
V
CC
=
Max, V
O
=
2.7V
V
IH
=
Min, V
IL
=
Max
V
CC
=
Max, V
O
=
0.4V
V
IH
=
Min, V
IL
=
Max
V
CC
=
Max (Note 10)
V
CC
=
Max, D
n
=
GND, OC
=
4.5V
−50
27
2.4
3.1
0.35
0.25
0.5
0.4
0.1
20
−0.4
20
−20
−225
45
mA
µA
mA
µA
µA
mA
mA
Min
Typ
(Note 9)
Max
−1.5
Units
V
V
V
Note 9:
All typicals are at V
CC
=
5V, T
A
=
25°C.
Note 10:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
DM74LS374 Switching Characteristics
at V
CC
=
5V and T
A
=
25°C
R
L
=
667Ω
Symbol
Parameter
C
L
=
45 pF
Min
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Output Enable Time
to HIGH Level Output
Output Enable Time
to LOW Level Output
Output Disable Time
from HIGH Level Output (Note 11)
Output Disable Time
from LOW Level Output (Note 11)
Note 11:
C
L
=
5 pF.
C
L
=
150 pF
Min
20
Max
Units
Max
35
28
28
28
28
20
25
MHz
32
38
44
44
ns
ns
ns
ns
ns
ns
5
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