1. Features
•
80C52 Compatible
– 8051 pin and instruction compatible
– Four 8-bit I/O ports
– Three 16-bit timer/counters
– 256 bytes scratchpad RAM
High-Speed Architecture
– 40 MHz @ 5V, 30MHz @ 3V
– X2 Speed Improvement capability (6 clocks/machine cycle)
– 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
– 60 MHz @ 5V, 40 MHz @ 3V)
Dual Data Pointer
On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K-bytes)
On-chip eXpanded RAM (XRAM) (256 or 768 bytes)
Programmable Clock Out and Up/Down Timer/Counter 2
Programmable Counter Array with
– High Speed Output,
– Compare / Capture,
– Pulse Width Modulator,
– Watchdog Timer Capabilities
Hardware Watchdog Timer (One-time enabled with Reset-Out)
2 extra 8-bit I/O ports available on RD2 with high pin count packages
Asynchronous port reset
Interrupt Structure with
– 7 Interrupt sources,
– 4 level priority interrupt system
Full duplex Enhanced UART
– Framing error detection
– Automatic address recognition
Low EMI (inhibit ALE)
Power Control modes
– Idle mode
– Power-down mode
– Power-off Flag
Once mode (On-chip Emulation)
Power supply: 4.5-5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70
o
C) and Industrial (-40 to 85
o
C)
Packages: PDIL40, PLCC44, VQFP44 1.4, PLCC68, VQFP64 1.4
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•
•
•
•
•
High
Performance
8-bit
Microcontroller
TS80C51RA2
TS80C51RD2
TS83C51RB2
TS83C51RC2
TS83C51RD2
TS87C51RB2
TS87C51RC2
TS87C51RD2
AT80C51RA2
AT80C51RD2
AT83C51RB2
AT83C51RC2
AT83C51RD2
AT87C51RB2
AT87C51RC2
AT87C51RD2
•
•
•
•
•
•
•
•
•
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2. Description
Atmel TS8xC51Rx2 is a high performance CMOS ROM, OTP, EPROM and ROMless
versions of the 80C51 CMOS single chip 8-bit microcontroller.
The TS8xC51Rx2 retains all features of the 80C51 with extended ROM/EPROM
capacity (16/32/64 Kbytes), 256 bytes of internal RAM, a 7-source , 4-level interrupt
system, an on-chip oscilator and three timer/counters.
In addition, the TS80C51Rx2 has a Programmable Counter Array, an XRAM of 256 or
768 bytes, a Hardware Watchdog Timer, a more versatile serial channel that facili-
Rev. 4188E–8051–08/06
tates multiprocessor communication (EUART) and an X2 speed improvement mechanism.
The fully static design of the TS80C51Rx2 allows to reduce system power consumption by bringing the clock frequency
down to any value, even DC, without loss of data.
The TS80C51Rx2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the
idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down
mode the RAM is saved and all other functions are inoperative.
PDIL40
PLCC44
VQFP44 1.4
TS80C51RA2
TS80C51RD2
TS83C51RB2
TS83C51RC2
TS83C51RD2
TS87C51RB2
TS87C51RC2
TS87C51RD2
ROM (bytes)
0
0
16k
32k
64k
0
0
0
EPROM (bytes)
0
0
0
0
0
16k
32k
64k
XRAM (bytes)
256
768
256
256
768
256
256
768
TOTAL RAM
(bytes)
512
1024
512
512
1024
512
512
1024
I/O
32
32
32
32
32
32
32
32
PLCC68
VQFP64 1.4
TS80C51RD2
TS83C51RD2
TS87C51RD2
ROM (bytes)
0
64k
0
EPROM (bytes)
0
0
64k
XRAM (bytes)
768
768
768
TOTAL RAM
(bytes)
1024
1024
1024
I/O
48
48
48
2
AT/TS8xC51Rx2
4188E–8051–08/06
4. SFR Mapping
The Special Function Registers (SFRs) of the TS80C51Rx2 fall into the following categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
• I/O port registers: P0, P1, P2, P3, P4, P5
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L,
RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• Power and clock control registers: PCON
• HDW Watchdog Timer Reset: WDTRST, WDTPRG
• PCA registers: CL, CH, CCAPiL, CCAPiH, CCON, CMOD, CCAPMi
• Interrupt system registers: IE, IP, IPH
• Others: AUXR, CKCON
4
AT/TS8xC51Rx2
4188E–8051–08/06
RF/Wirelessly
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