CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Operating Supply
Operating Supply
Shutdown Supply
GATE CONTROL OUTPUTS
HGATE dv/dt (No External Capacitor)
dv/dt
V
CC
= 12V
V
CC
= 5V
LGATE dv/dt (No External Capacitor)
dv/dt
V
CC
= 12V
V
CC
= 5V
HGATE Pull-Up Current
I
HGATE
V
CC
= 12V, V
HGATE
= 19V
V
CC
= 5V, V
HGATE
= 9.5V
HGATE Output Voltage
V
HGATE
V
CC
= 12V
V
CC
= 5V
LGATE Output Voltage
V
LGATE
V
CC
= 12V
V
CC
= 5V
ENABLE
Input Threshold Voltage
Enable Current
V
EN
I
EN
V
CC
= 12V
V
EN
= 5V
1
-
-
-
2.4
1
V
A
2.5
2.4
2.5
2.6
7.6
7.6
20.7
11.6
15.2
10.6
5
5
5
5
13.4
12.3
21.8
12.5
16.3
11.7
8.5
7.2
8.5
7.4
18.5
18.5
22.8
13.4
18.3
12.9
Vms
Vms
Vms
Vms
A
A
V
V
V
V
I
CC,12
I
CC,5
I
SHDN
V
EN
= 5V,V
CC
= 12V
V
EN
= 5V, V
CC
= 5V
V
EN
= 0V
-
-
-
1.6
0.77
-
2.3
1.1
1
mA
mA
A
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
FN4601 Rev 2.00
July 2004
Page 3 of 6
HIP1020
Typical Performance Curves
25
20
15
VOLTS
10
5
0
-5
0
10
20
30
40
50
MILLISECONDS
VOLTS
C1 = 22nF
22nF
NOTE 2
NOTE 3
C1 = 10nF
15
10
C1 = 22nF
5
0
-5
0
10
20
30
40
50
MILLISECONDS
25
20
NOTE 2
C1 = 10nF
NOTE 3
FIGURE 2. HGATE (PIN 4) TURNING ON WITH VCC = 12V
15
NOTE 2
10
C1 = 22nF
VOLTS
5
FIGURE 3. LGATE (PIN 3) TURNING ON WITH VCC = 12V
15
NOTE 2
NOTE 3
C1 = 10nF
NOTE 3
C1 = 10nF
10
VOLTS
C1 = 22nF
5
0
0
-5
0
10
20
30
40
50
MILLISECONDS
-5
0
10
20
30
40
50
MILLISECONDS
FIGURE 4. HGATE (PIN 4) TURNING ON WITH VCC = 5V
NOTES: Device is enabled at 10 milliseconds.
2. Pins 3 and 4 are unconnected.
FIGURE 5. LGATE (PIN 3)TURNING ON WITH VCC = 5V
3. Pins 3 and 4 are connected to the gates of “typical” high-performance N-Channel MOSFETs.
Application Information
The HIP1020 was designed specifically to address the
requirements of Device Bay peripherals. The small package,
low cost and integrated features make it the ideal component
for high-side power control of all three Device-Bay rail voltages
without using any additional components except for the
switching MOSFETs themselves. The integrated charge pump
supplies sufficient voltage to fully enhance the lower-cost N-
Channel power MOSFETs, and the internally-controlled turn-
on ramp provides soft switching for all types of loads.
Although the HIP1020 was developed with Device Bay in mind,
it has the versatility to perform in any situation where low-cost
load switching is required.
MOSFET Selection for Device Bay Peripherals
When selecting power MOSFETs for Device Bay (or any
similar application), two major concerns are the voltage drop
across the MOSFET and the thermal requirements imposed by
the particular application. Voltage drop across the MOSFET is
controlled by its on-state resistance, r
DS(ON)
, and the peak
current through the device, while the thermal requirements are
determined by several factors including ambient temperature,
amount of air flow if any, area of the copper mounting pad, the
thermal characteristics of the MOSFET and its package, and
the average current through the MOSFET.
FN4601 Rev 2.00
July 2004
Page 4 of 6
HIP1020
TABLE 1. DEVICE-BAY MOSFET SELECTION GUIDE FOR PERIPHERAL-POWER CONTROL
INTERSIL
PART NO.
HUF76105DK8
MOUNTING-PAD
AREA (IN
2
)
0.05
PACKAGE
SO-8
Dual
r
DS(ON)
(m)
63
51
48
HUF76113DK8
or
HUF76113T3ST
HUF76131SK8
0.08
0.05
SOT223
SO-8
Single
Single
0.05
SO-8
Dual
43
40
37
17
16
15
HUF76143S3S
NOTES:
4. Maximum-Average-Current level meets or exceeds the Device-Bay specified level for a 30s “peak”.
5. Maximum-Peak-Current level meets or exceeds the Device-Bay specified level for a 100s “transient”.
0.31
TO-263
Single
7
BUS
(VOLTAGE)
12
5
3.3
12
5
3.3
12
5
3.3
3.3
MAXIMUM
AVERAGE CURRENT
3A
(Note 4)
1A
1A
3A
(Note 4)
2A
1.5A
6A
(Note 4)
5A
(Note 4)
4A
9A
(Note 4)
MAXIMUM
PEAK CURRENT
7A
(Note 5)
2A
1.25A
11A
(Note 5)
2.5A
1.5A
25A
(Note 5)
6A
(Note 5)
4A
9A
(Note 5)
The MOSFETs in Table 1 were selected based on the
assumption that at most 2% the of the 5V or 3.3V-bus voltage
could appear across the 5V or 3.3V MOSFET, and that at most
4% of the 12V-bus voltage could appear across the 12V
MOSFET. The worst-case voltage drop occurs during a 100s
current transient given in the Maximum-Peak-Current column.
Longer transients may not be tolerable by the MOSFET
depending on its junction temperature prior to the transient.
In most cases, the given Mounting-Pad Area is required to
achieve the Maximum-Average-Current rating. It assumes 1-
oz. copper, zero air flow, and an ambient temperature not
exceeding 50
o
C. The Mounting-Pad Area is the approximate
area of a rectangle encompassing the MOSFET package and
its leads. The r
DS(ON)
numbers assume the device has
reached thermal equillibrium at the Maximum-Average-
Current. In some cases, the thermal capabilities as well as
r
DS(ON)
can be improved by using larger pads, heavier copper,
air flow, or lower ambient temperature.
which can effect the device’s operation as well as the operation
of any other device already connected and potentially the host
system itself. Without the dv/dt-activated clamp, a decoupling
capacitor would be needed between each power MOSFET
drain and ground using up valuable board space and adding
unnecessary cost. The HIP1020 solves this problem by
providing a path for capacitively-coupled current to reach
ground.
Increasing the Rise Time
The HIP1020 has an internal-ramping charge pump that
increases the voltage to the power MOSFETs in a predictable
controlled manner allowing soft turn on of most types of loads.
It is possible that some types of load would require slower turn
on. This could arise when a load has a large capacitive
component or for some other reason requires an
extraordinarily high starting current. Without the external
capacitor, C1 (see Figure 1), the ramp rate is about 5V/ms. A
capacitor between HGATE and ground will slow the rise time of
both gate voltages to a rate given by
I
HGATE
C1
= --------------------
-
dv
------
dt
(EQ.1)
Protection from Unwanted Turn On
A dv/dt-activated clamp circuit is internally connected to
LGATE (pin 4), and is active when the chip is not powered. It is
activated when the voltage on either LGATE or HGATE rises
too quickly, and it immediately provides a low-impedance
ground path for current from either gate pin.
The purpose of the dv/dt-activated clamp circuit is to prevent
unwanted turn on of the power MOSFETs during a hot
insertion event. When a Device-Bay peripheral is inserted into
the bay, the power pins on the peripheral are brought into
contact with the already-energized mating contacts in the bay.
This results in a very fast-rising voltage edge on the drains of
the power MOSFETs which can inject current through the
gate-to-drain capacitance and briefly turn on the power
MOSFET. The result is a momentary dip in the rail voltage
In Equation 1, C1 is the value of capacitor in Farads required to
achieve a rise rate of dv/dt in V/s, and I
HGATE
is current output
of pin 4 given in Amperes as shown in the “Electrical
Specifications” section of this data sheet. Figures 2 through 5
show gate voltage waveforms for selected values of C1.
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