FemtoClock
®
LVDS Programmable
Delay Line
ICS854S296I-33
DATA SHEET
General Description
The ICS854S296I-33 is a high performance LVDS Programmable
Delay Line. The delay can vary from 2.2ns to 12.5ns in 10ps steps.
The ICS854S296I-33 is characterized to operate from a 3.3V power
supply and is guaranteed over industrial temperature range.
The delay of the device varies in discrete steps based on a control
word. A 10-bit long control word sets the delay in 10ps increments.
Also, the input pins IN and nIN default to an equivalent low state
when left floating. The control register can accept CMOS or TTL
level signals.
Features
•
•
•
•
•
•
•
•
•
One LVDS level output
One differential clock input pair
Differential input clock (IN, nIN) can accept the following signaling
levels: LVPECL, LVDS, CML
Maximum frequency: 1.2GHz
Programmable Delay Range: 2.2ns to 12.5ns in 10ps steps
D[9:0] can accept LVPECL, LVCMOS or LVTTL levels
Full 3.3V supply voltages
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
GND
D7
D6
D2
D1
D4
D3
D5
32 31 30 29 28 27 26 25
D8
D9
RESERVED
IN
nIN
V
BB
V
EF
V
CF
1
2
3
4
5
6
7
8
9
GND
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
RESERVED
RESERVED
LEN
SETMAX
SETMIN
nEN
V
DD
GND
D0
V
DD
Q
nQ
V
DD
V
DD
F
TUNE
ICS854S296I-33
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm EPad
K Package
Top View
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
1
©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK
®
LVDS PROGRAMMABLE DELAY LINE
Block Diagram
IN
nIN
nEN
512
GD
0
1
256
GD
0
1
128
GD
0
1
64
GD
0
1
32
GD
0
1
GD = Gate Delay
0
1
16
GD
8
GD
0
1
4
GD
0
1
2
GD
0
1
1
GD
0
1
FTUNE
D[9:0]
LEN
SETMIN
SETMAX
10- bit
Latch
0
1
1
GD
Q
nQ
VBB
VCF
VEF
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
2
©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK
®
LVDS PROGRAMMABLE DELAY LINE
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 2, 23, 25,
26, 27, 29, 30,
31, 32
3, 14, 15
4
5
Name
D8, D9, D0, D1,
D2, D3, D4, D5,
D6, D7
RESERVED
IN
nIN
Input
Reserved
Input
Input
Pulldown
Pullup/
Pulldown
Type
Pulldown
Description
Parallel data input D[9:0].
Single-ended LVCMOS, LVTTL, LVPECL interface levels.
Reserved pins.
Non-inverting LVPECL differential input.
Inverting LVPECL differential input.
Reference voltage output. This pin can be used to rebias AC-coupled inputs
to IN and nIN. When used, de-couple to V
DD
using a 0.01 F capacitor. If not
used, leave floating.
Reference voltage output. See Table 3C.
Reference voltage input. The voltage driven on V
CF
sets the logic transition
threshold for D[9:0].
Power supply ground
Pulldown
D inputs LOAD and HOLD control input. When HIGH, latches the D[9:0] bits.
When LOW, the D[9:0] latches are transparent. Single-ended LVPECL
interface levels. See Table 3B.
Minimum delay set logic input. When HIGH, D[9:0] registers are reset. When
LOW, the delay is set by SETMAX or D[9:0]. Default is LOW when left
floating. Single-ended LVPECL interface levels. See Table 3D.
Maximum delay set logic input. When SETMAX is set HIGH and SETMIN is
set LOW, D[9:0] = 1111111111. When SETMAX is LOW, the delay is set by
SETMIN or D[9:0]. Default is low when left floating. Single-ended LVPECL
interface levels. See Table 3D.
Positive supply pins.
Pulldown
Single-ended control enable pin. When LOW, Q is delayed from IN.
When HIGH, Q is a differential LOW. Default is LOW when left floating.
Single-ended LVPECL interface levels. See Table 3A.
Fine tune delay control input. By varying the input voltage, it provides an
additional delay finer than the 10ps digital resolution.
Differential output pair. LVDS interface levels.
6
7
8
9, 24, 28
10
V
BB
V
EF
V
CF
GND
LEN
Output
Output
Input
Power
Input
11
SETMIN
Input
Pulldown
12
SETMAX
Input
Pulldown
13, 18, 19, 22
16
V
DD
nEN
Power
Input
Analog
Input
Output
17
20, 21
F
TUNE
nQ, Q
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
50
50
Maximum
Units
pF
k
k
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
3
©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK
®
LVDS PROGRAMMABLE DELAY LINE
Propagation Delay vs. F
TUNE
Voltage Graph
Function Tables
Table 3A. Delay Enable
nEN
0 (default)
1
Q, nQ
IN, nIN delayed
Q = LOW, nQ = HIGH
D[9:0] Value
XXXXXXXXXX
0000000000
SETMIN
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
SETMAX
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
Table 3D. Theoretical Delta Delay Values
Programmable
Delay
NOTE 1
(ps)
0
0 (default)
10
20
30
40
50
60
70
80
160
320
640
1280
2560
5120
10230
10240
Table 3B. Digital Control Latch
LEN
0 (default)
1
Latch Action
Pass Through D[9:0]
Latched D[9:0]
0000000001
0000000010
0000000011
0000000100
0000000101
Table 3C. V
CF
Connection for D[9:0] Logic Interface
Input
V
CF
V
CF
V
CF
V
CF
Connection
V
EF
(NOTE 1)
No Connect
1.5V source
D[9:0] Logic Interface
LVPECL
LVCMOS
LVTTL
0000000110
0000000111
0000001000
0000010000
0000100000
0001000000
NOTE 1: Short V
CF
(pin 8) to V
EF
(pin 7).
0010000000
0100000000
1000000000
1111111111
XXXXXXXXXX
NOTE 1: Fixed minimum delay not included.
NOTE: Refer to Table 6,
AC Characteristics,
for typical Step Delay
values.
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
4
©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK
®
LVDS PROGRAMMABLE DELAY LINE
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
39.5 C/W (0 mps)
-65 C to 150 C
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
No load, max V
DD
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
150
Units
V
mA
Table 5B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
D[9:0]
D[9:0]
V
DD
= V
IN
= 3.6V
V
DD
= 3.6V, V
IN
= 0V
-10
Test Conditions
Minimum
2.2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
μA
μA
Table 5C. LVPECL Differential DC Characteristics,
V
DD
= 3.3V ± 0.3V, GND = 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
BB
V
EF
Parameter
Input High Current
Input Low Current
nIN
Peak-to-Peak Voltage
Common Mode Range; NOTE 1
Output Voltage Reference
Mode Connection
IN, nIN
IN
Test Conditions
V
DD
= V
IN
= 3.6V
V
DD
= 3.6V, V
IN
= 0V
V
DD
= 3.6V, V
IN
= 0V
-10
-150
0.15
GND + 1.2
V
DD
– 1.55
V
DD
– 1.40
V
DD
– 1.35
V
DD
– 1.30
1.3
V
DD
V
DD
– 1.15
V
DD
– 1.20
Minimum
Typical
Maximum
150
Units
μA
μA
μA
V
V
V
V
NOTE 1: Common mode input voltage is defined as V
IH
.
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
5
©2014 Integrated Device Technology, Inc.
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