W79E532A/W79L532A Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
GENERAL DESCRIPTION .................................................................................................................... 2
FEATURES............................................................................................................................................ 2
PIN CONFIGURATIONS ....................................................................................................................... 3
PIN DESCRIPTION ............................................................................................................................... 4
FUNCTIONAL DESCRIPTION .............................................................................................................. 5
MEMORY ORGANIZATION .................................................................................................................. 7
INSTRUCTION .................................................................................................................................... 25
7.1
Instruction Timing .......................................................................................................... 25
POWER MANAGEMENT..................................................................................................................... 31
INTERRUPTS...................................................................................................................................... 35
PROGRAMMABLE TIMERS/COUNTERS .......................................................................................... 37
10.1
10.2
10.3
10.4
11.
Timer/Counters 0 & 1..................................................................................................... 37
Timer/Counter 2 ............................................................................................................. 40
Pulse Width Modulated Outputs (PWM)........................................................................ 43
Watchdog Timer ............................................................................................................ 46
Framing Error Detection ................................................................................................ 55
Multiprocessor Communications ................................................................................... 55
SERIAL PORT ..................................................................................................................................... 50
11.1
11.2
12.
13.
14.
TIMED ACCESS PROTECTION ......................................................................................................... 57
H/W REBOOT MODE (BOOT FROM 4K BYTES OF LDFLASH) ....................................................... 59
IN-SYSTEM PROGRAMMING ............................................................................................................ 60
14.1
14.2
15.
16.
17.
The Loader Program Locates at LDFlash Memory ....................................................... 60
The Loader Program Locates at APFlash Memory ....................................................... 60
H/W WRITER MODE........................................................................................................................... 60
SECURITY BITS.................................................................................................................................. 61
ELECTRICAL CHARACTERISTICS.................................................................................................... 62
17.1
17.2
17.3
18.
19.
20.
21.
Absolute Maximum Ratings ........................................................................................... 62
DC Characteristics......................................................................................................... 62
A.C. Characteristics ....................................................................................................... 64
TYPICAL APPLICATION CIRCUITS ................................................................................................... 69
PACKAGE DIMENSIONS.................................................................................................................... 70
APPLICATION NOTE .......................................................................................................................... 72
REVISION HISTORY........................................................................................................................... 77
-1-
Publication Release Date: January 03, 2007
Revision A7
W79E532A/W79L532A
1. GENERAL DESCRIPTION
The W79E(L)532 is a fast 8051 compatible microcontroller with a redesigned processor core without
wasted clock and memory cycles. As a result, it executes every 8051 instruction faster than the
original 8051 for the same crystal speed. Typically, the instruction executing time of W79E(L)532 is
1.5 to 3 times faster than that of traditional 8051, depending on the type of instruction. In general, the
overall performance is about 2.5 times better than the original for the same crystal speed. Giving the
same throughput with lower clock speed, power consumption has been improved. Consequently, the
W79E(L)532 is a fully static CMOS design; it can also be operated at a lower crystal clock. The
W79E(L)532 contains In-System Programmable (ISP) 128 KB bank-addressed Flash EPROM; 4KB
auxiliary Flash EPROM for loader program; on-chip 1 KB MOVX SRAM; power saving modes.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit CMOS microcontroller
High speed architecture of 4 clocks/machine cycle
Pin compatible with standard 80C52
Instruction-set compatible with MCS-51
Four 8-bit I/O Ports; Port 0 has internal pull-up resisters enabled by software
One extra 4-bit I/O port, chip select
Three 16-bit Timers
7 interrupt sources with two levels of priority
On-chip oscillator and clock circuitry
One enhanced full duplex serial port
Dual 64KB In-System Programmable Flash EPROM banks (APFlash0 and APFlash1)
4KB Auxiliary Flash EPROM for loader program (LDFlash)
256 bytes scratch-pad RAM
1 KB on-chip SRAM for MOVX instruction
Programmable Watchdog Timer
6 channels of 8 bit PWM
Software Reset
Software programmable access cycle to external RAM/peripherals
Code protection
Packages:
−
Lead Free (RoHS)DIP 40:
W79E532A40DL, W79L532A25DL
−
Lead Free (RoHS)PLCC 44: W79E532A40PL, W79L532A25PL
−
Lead Free (RoHS)QFP 44: W79E532A40FL, W79L532A25FL
-2-
W79E532A/W79L532A
DEVICE
OPERATING
FREQUENCY
OPERATING
VOLTAGE
PACKAGE
LEAD FREE(RoHS)
W79E532
W79L532
up to 40MHz
up to 20MHz
4.5V ~ 5.5V
3.0V ~ 5.5V
DIP44, PLCC44, QFP44
DIP44, PLCC44, QFP44
3. PIN CONFIGURATIONS
T2, PWM0, P1.0
T2EX, PWM1, P1.1
PWM2, P1.2
PWM3, P1.3
PWM4, P1.4
PWM5, P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
T1, P3.5
XTAL2
XTAL1
T2, PWM0, P1.0
T2EX, PWM1, P1.1
1
2
3
4
5
6
7
40
39
38
37
36
35
34
VDD
AD0, P0.0
AD1, P0.1
AD2, P0.2
AD3, P0.3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
PWM4, P1.4
PWM3, P1.3
PWM2, P1.2
T2EX, PWM1, P1.1
DIP 40-pin
8
9
10
11
12
13
14
15
16
17
18
19
20
33
32
31
30
29
28
27
26
25
24
23
22
21
T2, PWM0, P1.0
PWM4, P1.4
6
7
8
9
10
11
12
13
14
15
16
17
18
PWM3, P1.3
5
PWM2, P1.2
4
AD0, P0.0
AD1, P0.1
AD2, P0.2
AD3, P0.3
AD0, P0.0
AD1, P0.1
AD2, P0.2
AD3, P0.3
VDD
VDD
P4.2
P4.2
3
2
1
44
43
42
41
40
44
43
42
41
40
39
38
36
35
34
37
PWM5, P1.5
P1.6
P1.7
RST
RXD, P3.0
P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
39
38
37
36
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
PWM5, P1.5
P1.6
P1.7
RST
RXD, P3.0
P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
PLCC 44-pin
35
34
33
32
31
30
29
QFP 44-pin
29
28
27
26
25
24
23
19
P3.7, RD
20
21
22
23
24
25
26
27
28
P3.6, WR
XTAL2
XTAL1
VSS
P4.0
P2.0, A8
P2.1, A9
P2.2, A10
P2.3, A11
P2.4, A12
-3-
Publication Release Date: January 03, 2007
Revision A7
P3.6, WR
P3.7, RD
XTAL2
XTAL1
VSS
P4.0
P2.0, A8
P2.1, A9
P2.2, A10
P2.3, A11
W79E532A/W79L532A
4. PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTIONS
EA
I
EXTERNAL ACCESS ENABLE:
This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM
address and data will not be present on the bus if
EA
pin is high and the
program counter is within 128 KB area. Otherwise they will be present on the
bus.
PROGRAM STORE ENABLE:
PSEN
enables the external ROM data onto the
Port 0 address/data bus during fetch and MOVC operations. When internal
ROM access is performed, no
PSEN
strobe signal outputs from this pin.
ADDRESS LATCH ENABLE:
ALE is used to enable the address latch that
separates the address from the data on Port 0.
RESET:
A high on this pin for two machine cycles while the oscillator is running
resets the device.
CRYSTAL1:
This is the crystal oscillator input. This pin may be driven by an
external clock.
CRYSTAL2:
This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND:
Ground potential
POWER SUPPLY:
Supply voltage for operation.
PORT 0:
Port 0 is an open-drain bi-directional I/O port. This port also provides a
multiplexed low order address/data bus during accesses to external memory.
Port 0 has internal pull-up resisters enabled by software.
PORT 1:
Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture/Direction control
PORT 2:
Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
PORT 3:
Port 3 is a bi-directional I/O port with internal pull-ups. All bits have
alternate functions, which are described below:
RXD(P3.0) : Serial Port 0 input
TXD(P3.1) : Serial Port 0 output
PSEN
O
O
I
I
O
I
I
I/O
ALE
RST
XTAL1
XTAL2
V
SS
V
DD
P0.0
−
P0.7
P1.0
−
P1.7
I/O
P2.0
−
P2.7
I/O
P3.0
−
P3.7
I/O
INT0
(P3.2) : External Interrupt 0
INT1
(P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR
(P3.6) : External Data Memory Write Strobe
RD
(P3.7) : External Data Memory Read Strobe
P4.0
−
P4.3
I/O
PORT 4:
Port 4 is a 4-bit bi-directional I/O port. The P4.3 also provides the
alternate function
REBOOT
which is H/W reboot from LD flash.
* Note: TYPE
I : input, O: output, I/O: bi-directional.
-4-
W79E532A/W79L532A
5. FUNCTIONAL DESCRIPTION
The W79E(L)532 is 8052 pin compatible and instruction set compatible. It includes the resources of
the standard 8052 such as four 8-bit I/O Ports, three 16-bit timer/counters, full duplex serial port and
interrupt sources.
The W79E(L)532 features a faster running and better performance 8-bit CPU with a redesigned core
processor without wasted clock and memory cycles. it improves the performance not just by running at
high frequency but also by reducing the machine cycle duration from the standard 8052 period of
twelve clocks to four clock cycles for the majority of instructions. This improves performance by an
average of 1.5 to 3 times. It can also adjust the duration of the MOVX instruction (access to off-chip
data memory) between two machine cycles and nine machine cycles. This flexibility allows the
W79E(L)532 to work efficiently with both fast and slow RAMs and peripheral devices. In addition, the
W79E(L)532 contains on-chip 1KB MOVX SRAM, the address of which is between 0000H and
03FFH. It only can be accessed by MOVX instruction; this on-chip SRAM is optional under software
control.
The W79E(L)532 is an 8052 compatible device that gives the user the features of the original 8052
device, but with improved speed and power consumption characteristics. It has the same instruction
set as the 8051 family. While the original 8051 family was designed to operate at 12 clock periods per
machine cycle, the W79E(L)532 operates at a much reduced clock rate of only 4 clock periods per
machine cycle. This naturally speeds up the execution of instructions. Consequently, the W79E(L)532
can run at a higher speed as compared to the original 8052, even if the same crystal is used. Since
the W79E(L)532 is a fully static CMOS design, it can also be operated at a lower crystal clock, giving
the same throughput in terms of instruction execution, yet reducing the power consumption.
The 4 clocks per machine cycle feature in the W79E(L)532 is responsible for a three-fold increase in
execution speed. The W79E(L)532 has all the standard features of the 8052, and has a few extra
peripherals and features as well.
I/O Ports
The W79E(L)532 has four 8-bit ports and one extra 4-bit port. Port 0 can be used as an Address/Data
bus when external program is running or external memory/device is accessed by MOVC or MOVX
instruction. In these cases, it has strong pull-ups and pull-downs, and does not need any external pull-
ups. Otherwise it can be used as a general I/O port with open-drain circuit. Port 2 is used chiefly as
the upper 8-bits of the Address bus when port 0 is used as an address/data bus. It also has strong
pull-ups and pull-downs when it serves as an address bus. Port 1 and 3 act as I/O ports with alternate
functions. Port 4 serves as a general purpose I/O port as Port 1 and Port 3.
Serial I/O
The W79E(L)532 has one enhanced serial ports that are functionally similar to the serial port of the
original 8052 family. However the serial ports on the W79E(L)532 can operate in different modes in
order to obtain timing similarity as well. The serial port has the enhanced features of Automatic
Address recognition and Frame Error detection.
-5-
Publication Release Date: January 03, 2007
Revision A7
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