THCV213 and THCV214
LVDS SerDes transmitter and receiver
General Description
THCV213 and THCV214 are designed to support
pixel data transmission between the Host and Display.
The chipset can transmit 18bit data and 4bit control
data through only a single differential cable at a pixel
clock frequency from 5MHz to 40MHz.
By V-by-One® technologies, unique encoding
scheme and proprietary CDR technique, a link
synchronization is achieved without any external
frequency reference such as a crystal oscillator. It
drastically improves the cost and space of PCBs of a
display system.
THCV213 transmitter converts input data into a
single LVDS serial data stream with the embedded
clock. It supports pre-emphasis for a long cable
transmission.
THCV214 receiver extracts the clock from the
embedded clock and transforms the serial data stream
back into the parallel data.
To confirm the reliability of the link, several
functions are supported. THCV213 can transmit the
SYNC pattern which expedites the link establishment.
THCV214 has an indicator of its PLL status.
Features
Transmit 18bit data and 4bit control data via a
single differential cable
Wide frequency range: 5MHz to 40MHz
Support SYNC pattern and LOCK indicator
Pre Emphasis mode
Clock edge selectable
Dual Display mode
Power Down mode
Low power single 3.3V CMOS design
48pin TQFP
AEC-Q100 ESD Protection
Block Diagram
THCV213-214_Rev.2.40_E
Output Buffer
Input Buffer
Deserializer
Serializer
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Package Information
PART
THCV213-1TTN
THCV214-1TTN
THCV213-5TTN
THCV214-5TTN
TEMP.RANGE
0°C to 70°C
0°C to 70°C
-40°C to 85°C
-40°C to 85°C
PACKAGE
48pin TQFP
48pin TQFP
48pin TQFP
48pin TQFP
PIN Configuration
48Pin TQFP
VDD
D3
D2
D1
D0
GND
DE
SYNC0
SYNC1
SYNC2
VDD
INIT
D4
D5
D6
D7
D8
GND
D9
D10
D11
D12
D13
VDD
36
35
34
33
32
31
30
29
28
27
26
25
37
38
39
40
41
42
43
44
45
46
47
48
THCV213
24
23
22
21
20
19
18
17
16
15
14
13
GND
EDGE
GND
LVDSGND
TXOUT1-
TXOUT1+
LVDSGND
LVDSVDD
TXOUT2-
TXOUT2+
PLLGND
PLLVDD
LOCKN
VDD
SYNC2
SYNC1
SYNC0
DE
GND
GNDO
D0
D1
D2
D3
GND
EDGE
OE
LVDSGND
RXIN-
RXIN+
LVDSGND
LVDSVDD
RESERVED1
RESERVED2
PLLGND
PLLVDD
36
35
34
33
32
31
30
29
28
27
26
25
D14
D15
D16
D17
GND
CLKIN
VDD
PRBS
DUAL
PDWN
PRE0
PRE1
1
2
3
4
5
6
7
8
9
10
11
12
37
38
39
40
41
42
43
44
45
46
47
48
THCV214
24
23
22
21
20
19
18
17
16
15
14
13
VDDO
D4
D5
D6
D7
D8
GNDO
D9
D10
D11
D12
D13
THCV213-214_Rev.2.40_E
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MOD1
MOD0
PDWN
RESERVED0
VDDO
CLKOUT
GNDO
D17
D16
D15
D14
VDDO
THine Electronics, Inc.
1
2
3
4
5
6
7
8
9
10
11
12
PIN Description
THCV213 Pin Description
PIN Name
TXOUT1-,TXOUT1+
TXOUT2-,TXOUT2+
D0-D17
PIN No
20, 19
16, 15
32, 33, 34, 35,
37, 38, 39, 40,
41, 43, 44, 45,
46, 47, 1, 2, 3, 4
27, 28, 29
Type
LVDSOUT
LVDSOUT
IN
Description
LVDS output.
LVDS output for Dual Display mode.
Identical to TXOUT1+/-.
Hi-Z when Normal operation.
Data input.
Active if input DE=High
Sync input.
Active if input DE =Low.
Input sync data pulse must be wider than or equal to
two input clock periods.
Data Enable (DE) input.
Refer to Table2 for requirements.
Clock input.
5 MHz to 40MHz.
H: Normal operation.
L: Power Down, TXOUT1+/-, (TXOUT2+/-) are
Hi-Z.
Input clock triggering edge select.
H: Rise edge, L: Fall edge.
Select the level of pre-emphasis.
PRE1
PRE0
Description
L
L
w/o Pre-Emphasis
L
H
w/ 25% Pre-Emphasis
H
L
w/ 50% Pre-Emphasis
H
H
w/ 100% Pre-Emphasis
H: Triggers SYNC pattern output fromTXOUT1+/-
and (TXOUT2+/-), normally used in Shake
Hand mode.
L: Normal operation.
H: Dual Display mode
Both TXOUT1+/- and TXOUT2+/- enabled.
L: Normal operation
Only TXOUT1+/- enabled.
H: Internal test pattern generator is enabled.
Pseudo-Random Bit Sequence (PRBS) is
generated and is fed into input data latches.
Normally used for debug.
L: Normal operation.
Power supply pins for digital circuitry.
Ground pins for digital circuitry.
Power supply pin for LVDS output.
Ground pins for LVDS output.
Power supply pin for PLL circuitry.
Ground pin for PLL circuitry.
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SYNC2-SYNC0
IN
DE
CLKIN
PDWN
EDGE
PRE0, PRE1
30
6
10
23
11, 12
IN
IN
IN
IN
IN
INIT
25
IN
DUAL
9
IN
PRBS
8
IN
VDD
GND
LVDSVDD
LVDSGND
PLLVDD
PLLGND
7, 26, 36, 48
5, 22, 24, 31, 42
17
18, 21
13
14
Power
Power
Power
Power
Power
Power
THCV213-214_Rev.2.40_E
Copyright©2014 THine Electronics, Inc.
THCV214 Pin Description
PIN Name
RXIN-, RXIN+
D17-D0
PIN No
41, 42
8, 9, 10, 11, 13,
14, 15, 16, 17,
19, 20, 21, 22,
23, 25, 26, 27, 28
32, 33, 34
31
6
36
3
Type
LVDSIN
OUT
Description
LVDS input.
Data outputs.
SYNC0-SYNC2
DE
CLKOUT
LOCKN
PDWN
OUT
OUT
OUT
OUT
IN
EDGE
OE
38
39
IN
IN
MODE1, MOD0
1, 2
IN
Sync output.
Data Enable (DE) output.
Clock output.
Lock detects output.
H: Unlock, L: Lock.
Can be used as an input signal detector, too.
H: Normal operation.
L: Power Down, all outputs except LOCKN and
CLKOUT are held low. Refer to Fig9 for details.
(Note1)
Output clock triggering edge select.
H: Rise edge, L: Fall edge.
Output Enable.
(DE, SYNC0-SYNC2, D0-D17,CLKOUT)
H: Output disabled, all outputs are Hi-Z.
L: Output enabled. (Note1)
Select operation mode.
Both must be tied to GND.
MOD0
L
MOD1
L
RESERVED0
RESERVED1
RESERVED2
VDD
GND
LVDSVDD
LVDSGND
PLLVDD
PLLGND
VDDO
GNDO
4
45
46
35
30, 37
44
40,43
48
47
5, 12, 24
7, 18, 29
IN
IN
IN
Power
Power
Power
Power
Power
Power
Power
Power
Others
Must be tied to GND.
Must be tied to LVDSGND.
Must be tied to LVDSGND.
Power supply pin for digital circuitry.
Ground pins for digital circuitry.
Power supply pin for LVDS input.
Ground pins for LVDS input.
Power supply pin for PLL circuitry.
Ground pin for PLL circuitry.
Power supply pins for TTL output.
Ground pins for TTL output.
Normal Mode
Shake Hand Mode
Not Available
Note1: The state of outputs determined by the combination of OE and PDWN is as follow.
THCV213-214_Rev.2.40_E
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OE
L
L
H
H
Table1. Output State determined by OE and PDWN (THCV214)
PDWN
Output State
H
Normal Operation.
L
All outputs except LOCKN and CLKOUT are held low.
LOCKN is held high.
CLKOUT is driven high when EDGE input is high and is driven low
when EDGE input is low.
H
All outputs are Hi-Z.
L
All outputs are Hi-Z.
Table2. Requirements for DE input
DE = High
DE = Low
Min. 2t
TCIP
(See Fig. 5 for t
TCIP
)
Min. 50t
TCIP
(See Fig. 5 for t
TCIP
)
Max. 80usec
Min. 2t
TCIP
(See Fig. 5 for t
TCIP
)
Min. 2t
TCIP
(See Fig. 5 for t
TCIP
)
Operation Mode
Normal
Shake Hand
Absolute Maximum Ratings
Parameter
Supply Voltage (V
DD
)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Output Current
Junction Temperature
Storage Temperature Range
Reflow Peak Temperature / Time
Maximum Power Dissipation @+25°C
ESD Protection AEC-Q100-002(HBM)
ESD Protection AEC-Q100-003(MM)
ESD Protection AEC-Q100-011(CDM) (Corner.750)
Min
-0.3
-0.3
-0.3
-0.3
-30
-
-55
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
±2
±200
±500
Max
4.0
V
DD
+0.3
V
DD
+0.3
V
DD
+0.3
30
125
125
260/10
1.9
-
-
-
Unit
V
V
V
V
mA
°C
°C
°C/sec
W
kV
V
V
Operation Condition
Parameter
Supply Voltage
Operating Ambient Temperature
Consumer
Min
Typ
Max
3.0
3.3
3.6
0
-
70
Industrial
Min
Typ
Max
3.0
3.3
3.6
-40
-
85
Unit
V
°C
THCV213-214_Rev.2.40_E
Copyright©2014 THine Electronics, Inc.
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THine Electronics, Inc.
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