EEWORLDEEWORLDEEWORLD

Part Number

Search

591KD212M500DG

Description
SINGLE FREQUENCY XO, OE PIN 1
CategoryPassive components   
File Size416KB,16 Pages
ManufacturerSilicon Laboratories Inc
Download Datasheet Parametric View All

591KD212M500DG Online Shopping

Suppliers Part Number Price MOQ In stock  
591KD212M500DG - - View Buy Now

591KD212M500DG Overview

SINGLE FREQUENCY XO, OE PIN 1

591KD212M500DG Parametric

Parameter NameAttribute value
typeXO (Standard)
frequency212.5MHz
Functionenable/disable
outputCML
Voltage - Power1.8V
frequency stability±7ppm
Absolute pulling range (APR)-
Operating temperature-40°C ~ 85°C
Current - Power (maximum)110mA
grade-
Installation typesurface mount
Package/casing6-SMD, no leads
size/dimensions0.276" long x 0.197" wide (7.00mm x 5.00mm)
Height - Installation (maximum)0.071"(1.80mm)
Current - Power (disabled) (maximum)75mA
S i 5 9 0 / 5 91
1 ps M
AX
J
I T T E R
C
RYSTAL
O
SC ILLA TOR
(XO)
(10 M H
Z TO
810 MH
Z
)
Features
Available with any-frequency output
frequencies from 10 to 810 MHz
3rd generation DSPLL
®
with superior
jitter performance: 1 ps max jitter
Better frequency stability than SAW-
based oscillators
Internal fundamental mode crystal
ensures high reliability
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry Standard 5x7 and
3.2x5 mm packages
Pb-free/RoHS-compliant
–40 to +85 ºC operating
temperature range
Si5602
Applications
Ordering Information:
See page 8.
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
Test and measurement
Storage
FPGA/ASIC clock generation
Description
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry
to provide a low jitter clock at high frequencies. The Si590/591 supports any
frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique
crystal is required for each output frequency, the Si590/591 uses one fixed
crystal to provide a wide range of output frequencies. This IC based
approach allows the crystal resonator to provide exceptional frequency
stability and reliability. In addition, DSPLL clock synthesis provides superior
supply noise rejection, simplifying the task of generating low jitter clocks in
noisy environments typically found in communication systems. The
Si590/591 IC based XO is factory configurable for a wide variety of user
specifications including frequency, supply voltage, output format, and
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating long lead times associated with custom oscillators.
Pin Assignments:
See page 7.
(Top View)
NC
1
6
V
DD
OE
2
5
CLK–
GND
3
4
CLK+
Si590 (LVDS/LVPECL/CML)
OE
1
6
V
DD
Functional Block Diagram
NC
2
5
NC
V
DD
CLK– CLK+
GND
3
4
CLK
17 k
*
Any-rate
10–810 MHz
DSPLL
®
Clock
Synthesis
Si590 (CMOS)
OE
Fixed
Frequency
XO
OE
1
6
V
DD
NC
2
5
CLK–
17 k
*
GND
3
4
CLK+
GND
*Note: Output Enable High/Low Options Available – See Ordering Information
Si591 (LVDS/LVPECL/CML)
Rev. 1.2 6/18
Copyright © 2018 by Silicon Laboratories
Si590/591
How to access external registers in atmegma48
[i=s] This post was last edited by paulhyde on 2014-9-15 09:18 [/i] Asking for advice: How to access external registers in atmegma48? What should I do if Da0832 uses double buffering?...
liu5013 Electronics Design Contest
I would like to ask what tool to use to open the mobile phone software BIN file. Does anyone know?
I would like to ask what tool to use to open the mobile phone software BIN file. Does anyone know?...
xwj521 Embedded System
The device query function is not available?
I searched for devices on our website today, but the following error occurred and I could not search anymore. “ Service Unavailable ”I don't know if this is the right reaction, please solve it, haha...
HOHO Suggestions & Announcements
Recruiting part-time HyperLynx and other lecturers
Recruiting part-time HyperLynx and other related lecturers, short period, weekends. If you want to earn some extra money, accumulate resources, and enrich your life, please contact me. You are require...
hehe234 Recruitment
Synchronous debugging of multiple 6678 chips
Dear experts, I would like to ask about the synchronous debugging of multiple C6678 chips: I plan to make two boards, each board integrates two C6678 chips, and the communication between the boards is...
sunqianqing2005 TI Technology Forum
Basic knowledge for hardware engineers
Basic knowledge for hardware engineers Purpose: To understand and master the most basic knowledge to become a qualified hardware engineer based on practical experience and actual projects. 1) Basic de...
linda_xia Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 824  1961  2191  684  944  17  40  45  14  19 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号