514PBB000436BAGR datasheet, PDF

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514PBB000436BAGR: DescriptionOSC XO 10.0000MHZ CMOS DUAL SMD; CategoryPassive components; File Size746KB，38 Pages; ManufacturerSilicon Laboratories Inc

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514PBB000436BAGR Overview

OSC XO 10.0000MHZ CMOS DUAL SMD

514PBB000436BAGR Parametric

Parameter Name	Attribute value
type	XO (Standard)
frequency	10MHz
Function	Enable/Disable (Reprogrammable)
output	CMOS, dual channel (synchronous)
Voltage - Power	2.25 V ~ 2.75 V
frequency stability	±25ppm
Absolute pulling range (APR)	-
Operating temperature	-40°C ~ 85°C
Current - Power (maximum)	26mA
grade	-
Installation type	surface mount
Package/casing	6-SMD, no leads
size/dimensions	0.197" long x 0.126" wide (5.00mm x 3.20mm)

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Si514

N Y

-F

REQUENCY

C P

R OG R A MM A B L E

X O ( 1 0 0 k H

Features



250 MH

)

Programmable to any frequency



from 100 kHz to 250 MHz

0.026 ppb frequency tuning



resolution



Glitch suppression on OE, power

on and frequency transitions



Low jitter operation

2- to 4-week lead times



Total stability includes 10-year

aging



Comprehensive production test

coverage includes crystal ESR and

DLD

On-chip LDO for power supply

noise filtering

3.3, 2.5, or 1.8 V operation

Differential (LVPECL, LVDS,

HCSL) or CMOS output options

Optional integrated 1:2 CMOS

fanout buffer

Industry standard 5x7, 3.2x5, and

2.5x3.2 mm packages

–40 to 85

C operation

Si5602

5x7mm, 3.2x5mm

2.5x3.2mm

Ordering Information:

See page 28.

Applications

All-digital PLLs



DAC+ VCXO replacement



SONET/SDH/OTN



3G-SDI/HD-SDI/SDI



Pin Assignments:

See page 27.

Datacom



Industrial automation



FPGA/ASIC clock generation



FPGA synchronization



SDA

SCL

GND

Description

The Si514 user-programmable I

C XO utilizes Silicon Laboratories' advanced PLL

technology to provide any frequency from 100 kHz to 250 MHz with programming

resolution of 0.026 parts per billion. The Si514 uses a single integrated crystal and

Silicon Labs’ proprietary DSPLL synthesizer to generate any frequency across this

range using simple I

C commands. Ultra-fine tuning resolution replaces DACs and

VCXOs with an all-digital PLL solution that improves performance where

synchronization is necessary or in free-running reference clock applications. This

solution provides superior supply noise rejection, simplifying low jitter clock

generation in noisy environments. Crystal ESR and DLD are individually

production-tested to guarantee performance and enhance reliability.

The Si514 is factory-configurable for a wide variety of user specifications, including

startup frequency, I

C address, supply voltage, output format, and stability. Specific

configurations are factory-programmed at time of shipment, eliminating long lead

times and non-recurring engineering charges associated with custom frequency

oscillators.

CLK–

CLK+

Functional Block Diagram

Rev. 1.2 6/18

Si514

Si514

ABLE O F

ONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . . 11

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2. Programming a Small Frequency Change (sub ±1000 ppm) . . . . . . . . . . . . . . . . . . 13

3.3. Programming a Large Frequency Change (> ±1000 ppm) . . . . . . . . . . . . . . . . . . . . 14

4. All-Digital PLL Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5. User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2. Register Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1. Dual CMOS (1:2 Fanout Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

10. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

11. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

12. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

13. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

14.1. Si514 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Rev. 1.2

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