EPF10K100ABC600-3N datasheet, PDF

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EPF10K100ABC600-3N: DescriptionLoadable PLD, 0.8ns, CMOS, PBGA600, BGA-600; CategoryProgrammable logic Programmable logic devices; File Size2MB，143 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

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EPF10K100ABC600-3N Overview

Loadable PLD, 0.8ns, CMOS, PBGA600, BGA-600

EPF10K100ABC600-3N Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Intel
package instruction	BGA,
Reach Compliance Code	compliant
Is Samacsys	N
JESD-30 code	S-PBGA-B600
JESD-609 code	e1
length	45 mm
Humidity sensitivity level	3
Dedicated input times	4
Number of I/O lines	406
Number of terminals	600
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4 DEDICATED INPUTS, 406 I/O
Output function	REGISTERED
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	245
Programmable logic type	LOADABLE PLD
propagation delay	0.8 ns
Certification status	Not Qualified
Maximum seat height	1.93 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	45 mm
Base Number Matches	1

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Includes

FLEX 10KA

FLEX 10K

Embedded Programmable

Logic Device Family

Data Sheet

March 2001, ver. 4.1

Features...

The industry’s first embedded programmable logic device (PLD)

family, providing System-on-a-Programmable-Chip (SOPC)

integration

–

Embedded array for implementing megafunctions, such as

efficient memory and specialized logic functions

–

Logic array for general logic functions

High density

–

10,000 to 250,000 typical gates (see

Tables 1

and

–

Up to 40,960 RAM bits; 2,048 bits per embedded array block

(EAB), all of which can be used without reducing logic capacity

System-level features

–

MultiVolt

I/O interface support

–

5.0-V tolerant input pins in FLEX

10KA devices

–

Low power consumption (typical specification less than 0.5 mA

in standby mode for most devices)

–

FLEX 10K and FLEX 10KA devices support peripheral

component interconnect Special Interest Group (PCI SIG)

PCI

Local Bus Specification, Revision 2.2

–

FLEX 10KA devices include pull-up clamping diode, selectable

on a pin-by-pin basis for 3.3-V PCI compliance

–

Select FLEX 10KA devices support 5.0-V PCI buses with eight or

fewer loads

–

Built-in Joint Test Action Group (JTAG) boundary-scan test

(BST) circuitry compliant with IEEE Std. 1149.1-1990, available

without consuming any device logic

Table 1. FLEX 10K Device Features

Feature

Typical gates (logic and RAM)

(1)

Maximum system gates

Logic elements (LEs)

Logic array blocks (LABs)

Embedded array blocks (EABs)

Total RAM bits

Maximum user I/O pins

EPF10K10

EPF10K10A

10,000

31,000

576

6,144

150

EPF10K20

20,000

63,000

1,152

144

12,288

189

EPF10K30

EPF10K30A

30,000

69,000

1,728

216

12,288

246

EPF10K40

40,000

93,000

2,304

288

16,384

189

EPF10K50

EPF10K50V

50,000

116,000

2,880

360

20,480

310

Altera Corporation

A-DS-F10K-04.1

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