74HC163; 74HCT163
Rev. 5 — 12 October 2018
Presettable synchronous 4-bit binary counter; synchronous
reset
Product data sheet
1. General description
The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head
carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the
positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to
a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes
the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of
the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A
LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition
on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and
CEP. This synchronous reset feature enables the designer to modify the maximum count with
only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters.
Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal
count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded
stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess of V
CC
.
The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock
frequency for the cascaded counters according to the following formula:
2. Features and benefits
•
•
Complies with JEDEC standard no. 7A
Input levels:
•
For 74HC163: CMOS level
•
For 74HCT163: TTL level
Synchronous counting and loading
2 count enable inputs for n-bit cascading
Synchronous reset
Positive-edge triggered clock
ESD protection:
•
HBM JESD22-A114F exceeds 2 000 V
•
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
•
•
•
•
•
•
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC163D
74HCT163D
-40 °C to +125 °C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT109-1
Nexperia
74HC163; 74HCT163
Presettable synchronous 4-bit binary counter; synchronous reset
Package
Temperature range
Name
SSOP16
TSSOP16
Description
plastic shrink small outline package;
16 leads; body width 5.3 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT338-1
SOT403-1
-40 °C to +125 °C
-40 °C to +125 °C
Type number
74HC163DB
74HCT163DB
74HC163PW
74HCT163PW
4. Functional diagram
9
3
4
D1
5
D2
6
D3
3
D0
9 PE
1 MR
TC
15
4
D1
5
D2
6
D3
7
10
2
1
PE D0
CEP
CET
CP
MR
PARALLEL
LOAD CIRCUITRY
10 CET
7 CEP
D
INH
CP
TC 15
Q0 Q1 Q2 Q3
14
13
12
11
aaa-012184
2 CP
BINARY
COUNTER
Q1
13
Q2
12
Q3
11
Q0
14
aaa-012186
Fig. 1.
Logic symbol
1
9
7
10
2
3
4
5
6
Fig. 2.
CTR4
Functional diagram
2R
M1
G3
G4
C2/1,3,4+
1,2D
14
13
12
11
4CT = 15
15
aaa-012185
Fig. 3.
IEC logic symbol
74HC_HCT163
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 5 — 12 October 2018
2 / 20
Nexperia
74HC163; 74HCT163
Presettable synchronous 4-bit binary counter; synchronous reset
5. Pinning information
5.1. Pinning
74HC163
74HCT163
MR
CP
D0
D1
D2
D3
CEP
GND
1
2
3
4
5
6
7
8
aaa-012181
16 V
CC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
9
PE
MR
CP
D0
D1
D2
D3
CEP
GND
1
2
3
4
5
6
7
8
74HC163
74HCT163
16 V
CC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
9
aaa-012182
PE
Fig. 5.
Pin configuration SOT109-1 (SO16)
Fig. 6.
Pin configuration SOT338-1 (SSOP16) and
SOT403-1 (TSSOP16)
5.2. Pin description
Table 2. Pin description
Symbol
MR
CP
D0, D1, D2, D3
CEP
GND
PE
CET
Q0, Q1, Q2, Q3
TC
V
CC
Pin
1
2
3, 4, 5, 6
7
8
9
10
14, 13, 12, 11
15
16
Description
synchronous master reset (active LOW)
clock input (LOW-to-HIGH, edge triggered)
data input
count enable input
ground (0 V)
parallel enable input (active LOW)
count enable carry input
flip-flop output
terminal count output
supply voltage
74HC_HCT163
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 5 — 12 October 2018
4 / 20
Nexperia
74HC163; 74HCT163
Presettable synchronous 4-bit binary counter; synchronous reset
6. Functional description
Table 3. Function table[1]
Operating mode
Reset (clear)
Parallel load
Count
Hold (do nothing)
Inputs
MR
I
h
h
h
h
h
[1]
Outputs
CP
↑
↑
↑
↑
X
X
CEP
X
X
X
h
I
X
CET
X
X
X
h
X
I
PE
X
I
I
h
h
h
Dn
X
I
h
X
X
X
Qn
L
L
H
count
qn
qn
L
L
TC
L
L
L
The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH);
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition;
X = don’t care;
↑ = LOW-to-HIGH clock transition.
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
aaa-012187
Fig. 7.
State diagram
74HC_HCT163
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 5 — 12 October 2018
5 / 20
Embedded System
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