PCA9665; PCA9665A
Fm+ parallel bus to I
2
C-bus controller
Rev. 4 — 29 September 2011
Product data sheet
1. General description
The PCA9665/PCA9665A serves as an interface between most standard parallel-bus
microcontrollers/microprocessors and the serial I
2
C-bus and allows the parallel bus
system to communicate bidirectionally with the I
2
C-bus. The PCA9665/PCA9665A can
operate as a master or a slave and can be a transmitter or receiver. Communication with
the I
2
C-bus is carried out on a Byte or Buffered mode using interrupt or polled handshake.
The PCA9665/PCA9665A controls all the I
2
C-bus specific sequences, protocol, arbitration
and timing with no external timing element required.
The PCA9665 and PCA9665A have the same footprint as the PCA9564 with additional
features:
•
•
•
•
•
1 MHz transmission speeds
Up to 25 mA drive capability on SCL/SDA
68-byte buffer
I
2
C-bus General Call
Software reset on the parallel bus
2. Features and benefits
Parallel-bus to I
2
C-bus protocol converter and interface
Both master and slave functions
Multi-master capability
Internal oscillator trimmed to 15 % accuracy reduces external components
1 Mbit/s and up to 25 mA SCL/SDA I
OL
(Fast-mode Plus (Fm+)) capability
I
2
C-bus General Call capability
Software reset on parallel bus
68-byte data buffer
Operating supply voltage: 2.3 V to 3.6 V
5 V tolerant I/Os
Standard-mode and Fast-mode I
2
C-bus capable and compatible with SMBus
PCA9665A ‘glitch-free’ restart is suitable for use with buffer drivers
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered:
PCA9665: SO20, TSSOP20, HVQFN20
PCA9665A: TSSOP20
NXP Semiconductors
PCA9665; PCA9665A
Fm+ parallel bus to I
2
C-bus controller
3. Applications
Add I
2
C-bus port to controllers/processors that do not have one
Add additional I
2
C-bus ports to controllers/processors that need multiple I
2
C-bus ports
Converts 8 bits of parallel data to serial data stream to prevent having to run a large
number of traces across the entire printed-circuit board
4. Ordering information
Table 1.
Ordering information
T
amb
=
40
C to +85
C.
Type number
PCA9665BS
PCA9665D
PCA9665PW
PCA9665APW
Topside
mark
9665
PCA9665D
PCA9665
CA9665A
Package
Name
HVQFN20
SO20
TSSOP20
TSSOP20
Description
Version
plastic thermal enhanced very thin quad flat package; no leads; SOT662-1
20 terminals; body 5
5
0.85 mm
plastic small outline package; 20 leads; body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT163-1
SOT360-1
SOT360-1
PCA9665_PCA9665A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 29 September 2011
2 of 92
NXP Semiconductors
PCA9665; PCA9665A
Fm+ parallel bus to I
2
C-bus controller
5. Block diagram
data
D7
D6
D5
D4
D3
D2
D1
D0
PCA9665/PCA9665A
SDA
BUS BUFFER
FILTER
SDA CONTROL
68-BYTE
BUFFER
–
AA ENSIO STA STO SI
ST5
SCL
FILTER
ST4
ST3
ST2
ST1
ST0
0
0
0
0
I2CSTA – status register – read only
AA
ENSIO
STA
STO
SI
–
–
MODE
–
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
1
direct registers
A1
A0
I2CDAT – data register – read/write
–
–
–
IP2
IP1
IP0
INDPTR – indirect address pointer – write only
0
0
SCL CONTROL
I2CCON – control register – read/write
BIT7
BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
INDIRECT – indirect register access – read/write
1
1
1
0
ENSIO STA STO SI
LB
BC6
BC5
BC4
BC3
BC2
BC1
BC0
indirect registers
INDPTR
00h
I2CCOUNT – byte count – read/write
AD7
AD6
AD5
AD4
AD3
AD2
AD1
I2CADR – own address – read/write
L6
L5
L4
L3
L2
L1
GC
01h
L0
02h
L7
I2CSCLL – SCL LOW period – read/write
H7
H6
H5
H4
H3
H2
H1
H0
03h
BIT0
04h
IR0
05h
AC0
06h
I2CSCLH – SCL HIGH period – read/write
TE
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
I2CTO – TIMEOUT register – read/write
IR7
IR6
IR5
IR4
IR3
IR2
IR1
I2CPRESET – software reset register – write only
–
–
–
–
–
–
AC1
I2CMODE – I
2
C-bus mode register – read/write
CONTROL BLOCK
CLOCK SELECTOR
OSCILLATOR
INTERRUPT CONTROL
POWER-ON
RESET
002aab023
CE
WR
RD
INT
control signals
RESET
A1
A0
V
DD
Fig 1.
Block diagram of PCA9665/PCA9665A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
PCA9665_PCA9665A
Product data sheet
Rev. 4 — 29 September 2011
3 of 92
NXP Semiconductors
PCA9665; PCA9665A
Fm+ parallel bus to I
2
C-bus controller
6. Pinning information
6.1 Pinning
D0
D1
D2
D3
D4
D5
D6
D7
i.c.
1
2
3
4
5
6
7
8
9
20 V
DD
19 SDA
18 SCL
17 RESET
16 INT
15 A1
14 A0
13 CE
12 RD
11 WR
002aab020
D0
D1
D2
D3
D4
D5
D6
D7
i.c.
1
2
3
4
5
6
7
8
9
20 V
DD
19 SDA
18 SCL
17 RESET
16 INT
15 A1
14 A0
13 CE
12 RD
11 WR
002aab021
PCA9665D
PCA9665PW
PCA9665APW
V
SS
10
V
SS
10
Fig 2.
Pin configuration for SO20
20 D2
19 D1
terminal 1
index area
Fig 3.
16 SDA
17 V
DD
18 D0
Pin configuration for TSSOP20
D3
D4
D5
D6
D7
1
2
3
4
5
CE 10
6
7
8
9
15 SCL
14 RESET
PCA9665BS
13 INT
12 A1
11 A0
WR
V
SS
RD
i.c.
002aab022
Transparent top view
Fig 4.
Pin configuration for HVQFN20
PCA9665_PCA9665A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 29 September 2011
4 of 92
NXP Semiconductors
PCA9665; PCA9665A
Fm+ parallel bus to I
2
C-bus controller
6.2 Pin description
Table 2.
Pin description
Type
HVQFN20
18
19
20
1
2
3
4
5
6
7
[1]
8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
power
I
internally connected:
must be left floating (pulled
LOW internally)
Supply ground
Write strobe:
When LOW and CE is also LOW, the
content of the data bus is loaded into the addressed
register. Data are latched on the rising edge of either
WR or CE.
Read strobe:
When LOW and CE is also LOW,
causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on
the falling edge of RD.
Chip Enable:
Active LOW input signal. When LOW,
data transfers between the CPU and the bus
controller are enabled on D0 to D7 as controlled by
the WR, RD and A0 to A1 inputs. When HIGH,
places the D0 to D7 lines in the 3-state condition.
Data are written into the addressed register on rising
edge of either CE or WR.
A0
A1
INT
RESET
14
15
16
17
11
12
13
14
I
I
O
I
Address inputs:
Selects the bus controller’s internal
registers and ports for read/write operations.
Interrupt request:
Active LOW, open-drain, output.
This pin requires a pull-up device.
Reset:
Active LOW input. A LOW level clears
internal registers and resets the I
2
C-bus state
machine.
I
2
C-bus serial clock input/output (open-drain).
This pin requires a pull-up device.
I
2
C-bus serial data input/output (open-drain). This pin
requires a pull-up device.
Power supply:
2.3 V to 3.6 V
Data bus:
Bidirectional 3-state data bus used to
transfer commands, data and status between the bus
controller and the CPU. D0 is the least significant bit.
Description
SO20,
TSSOP20
D0
D1
D2
D3
D4
D5
D6
D7
i.c.
V
SS
WR
1
2
3
4
5
6
7
8
9
10
11
Symbol Pin
RD
12
9
I
CE
13
10
I
SCL
SDA
V
DD
[1]
18
19
20
15
16
17
I/O
I/O
power
HVQFN20 package die supply ground is connected to both the V
SS
pin and the exposed center pad. The
V
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
PCA9665_PCA9665A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 29 September 2011
5 of 92
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