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596AG000346DG

Description
VCXO; DIFF/SE; DUAL FREQ; 10-810
CategoryPassive components   
File Size418KB,17 Pages
ManufacturerSilicon Laboratories Inc
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596AG000346DG Overview

VCXO; DIFF/SE; DUAL FREQ; 10-810

596AG000346DG Parametric

Parameter NameAttribute value
typeVCXO
Frequency - Output 110MHz
Frequency - Output 210MHz
Frequency - Output 3-
Frequency - Output 4-
Function-
outputLVPECL
Voltage - Power3.3V
frequency stability±50ppm
Operating temperature-40°C ~ 85°C
Current - Power (maximum)135mA
size/dimensions0.276" long x 0.197" wide (7.00mm x 5.00mm)
high0.071"(1.80mm)
Package/casing6-SMD, no leads
Si596
D
U A L
F
REQUENCY
V
OLTAGE
- C
ON TROLLED
C
R Y S TA L
O
SCILLATOR
( V C X O ) 1 0
TO
810 MH
Z
Features
Available with any-rate output
frequencies from 10 to 810 MHz
Two selectable output frequencies
3
rd
generation DSPLL
®
with
superior jitter performance
Internal fixed fundamental mode
crystal frequency ensures high
reliability and low aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry standard 5x7 and
3.2x5 mm packages
Pb-free/RoHS-compliant
–40 to +85 ºC operating range
Si5602
Applications
Ordering Information:
See page 9.
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
FTTx
Clock recovery and jitter cleanup PLLs
FPGA/ASIC clock generation
Description
The Si596 dual-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a low-jitter clock at high frequencies. The Si596
is available with any-rate output frequency from 10 to 810 MHz. Unlike
traditional VCXOs, where a different crystal is required for each output
frequency, the Si596 uses one fixed crystal to provide a wide range of output
frequencies. This IC-based approach allows the crystal resonator to provide
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides supply noise rejection, simplifying the task of generating
low-jitter clocks in noisy environments. The Si596 IC-based VCXO is
factory-configurable for a wide variety of user specifications including
frequency, supply voltage, output format, tuning slope, and absolute pull
range (APR). Specific configurations are factory programmed at time of
shipment, thereby eliminating the long lead times associated with custom
oscillators.
Pin Assignments:
See page 8.
(Top View)
V
C
V
DD
1
6
FS
GND
2
5
CLK–
3
4
CLK+
Functional Block Diagram
V
DD
CLK–
CLK+
Fixed
Frequency
XO
Any-rate
10–810 MHz
DSPLL
®
Clock Synthesis
ADC
Vc
FS
GND
Rev. 1.2 6/18
Copyright © 2018 by Silicon Laboratories
Si596
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